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AT88SC3216C

CryptoMemory 32 Kbit

Atmel Corporation 

AT88SC3216C

Figure 3.

SCL

2. Look for SDA high in each cycle while SCL is high.

3. Create a start condition.

Bus Timing for 2 wire communications: SCL: Serial Clock, SDA – Serial Data I/O

tF

tLOW

tHIGH

tLOW

SDA IN

tSU.STA

tHD.STA

tHD.DAT

tSU.DAT

tAA

tDH

SDA OUT

tR

tSU.STO

tBUF

Figure 4. Write Cycle Timing: SCL: Serial Clock, SDA – Serial Data I/O

SCL

SDA

8th BIT

ACK

WORDn

STOP

CONDITION

(1)

twr

START

CONDITION

Note: The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal

clear/write cycle.

7

5014KS–SMEM–08/09

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