AT25F512B-SSH-B Ver la hoja de datos (PDF) - Atmel Corporation
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AT25F512B-SSH-B Datasheet PDF : 34 Pages
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The WEL bit in the Status Register will be reset back to the logical “0” state if the erase cycle
aborts due to an incomplete address being sent, the CS pin being deasserted on uneven byte
boundaries, or because a memory location within the region to be erased is protected.
While the device is executing a successful erase cycle, the Status Register can be read and will
indicate that the device is busy. For faster throughput, it is recommended that the Status Regis-
ter be polled rather than waiting the tBLKE time to determine if the device has finished erasing. At
some point before the erase cycle completes, the WEL bit in the Status Register will be reset
back to the logical “0” state.
The device also incorporates an intelligent erase algorithm that can detect when a byte location
fails to erase properly. If an erase error occurs, it will be indicated by the EPE bit in the Status
Register.
Figure 8-3. Block Erase
CS
SCK
SI
SO
0 1 2 3 4 5 6 7 8 9 10 11 12
26 27 28 29 30 31
OPCODE
ADDRESS BITS A23-A0
CCCCCCCCAAAAAA
MSB
MSB
AAAAAA
HIGH-IMPEDANCE
8.3 Chip Erase
The entire memory array can be erased in a single operation by using the Chip Erase command.
Before a Chip Erase command can be started, the Write Enable command must have been pre-
viously issued to the device to set the WEL bit of the Status Register to a logical “1” state.
Three opcodes (60h, 62h, and C7h) can be used for the Chip Erase command. There is no dif-
ference in device functionality when utilizing the three opcodes, so they can be used
interchangeably. To perform a Chip Erase, one of the three opcodes must be clocked into the
device. Since the entire memory array is to be erased, no address bytes need to be clocked into
the device, and any data clocked in after the opcode will be ignored. When the CS pin is deas-
serted, the device will erase the entire memory array. The erasing of the device is internally self-
timed and should take place in a time of tCHPE.
The complete opcode must be clocked into the device before the CS pin is deasserted, and the
CS pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, no
erase will be performed. In addition, if the memory array is in the protected state, then the Chip
Erase command will not be executed, and the device will return to the idle state once the CS pin
has been deasserted. The WEL bit in the Status Register will be reset back to the logical “0”
state if the CS pin is deasserted on uneven byte boundaries or if the memory is in the protected
state.
While the device is executing a successful erase cycle, the Status Register can be read and will
indicate that the device is busy. For faster throughput, it is recommended that the Status Regis-
ter be polled rather than waiting the tCHPE time to determine if the device has finished erasing. At
10 AT25F512B [Preliminary]
3689C–DFLASH–12/08
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