4. Memory Array
To provide the greatest flexibility, the memory array of the AT25F512B can be erased in three
levels of granularity including a full chip erase. The size of the erase blocks is optimized for both
code and data storage applications, allowing both code and data segments to reside in their own
erase regions. The Memory Architecture Diagram illustrates the breakdown of each erase level.
Figure 4-1. Memory Architecture Diagram
4 AT25F512B [Preliminary]
3689C–DFLASH–12/08