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Fabricante

ADSP-21992
(Rev.:RevPrA)

Mixed Signal DSP Controller With CAN

Analog Devices 

PRELIMINARY TECHNICAL DATA

August 2002

For current information contact Analog Devices at (781) 937-1799

ADSP-21992

GND

JTAG

CONNECTOR

1

2

EMU

3

KEY (NO PIN)

5

BTMS

4

GND

6

TMS

7

BTCK

9

BTRST

8

TCK

10

TRST

11

BTDI

12

TDI

13

GND

14

TDO

TOP VIEW

VDD

DSP

P0

DSP

P1

TDI

TDO

TDI

TDO

DSP

P#

TDI

TDO

BUFFERS

Figure 9. Multiple-DSP JTAG-Connections, Buffered

Layout Requirements

All JTAG signals (TCK, TMS, TDI, TDO, EMU, and

TRST) should be treated as critical route signals. This

means pay special attention when routing these signals.

Specify a controlled impedance requirement for each route

(value depends on your circuit board - typically 50-75⍀).

Keep crosstalk and inductance to a minimum on these lines

by using a good ground plane and by routing away from

other high noise signals such as clock lines. Keep these

routes as short and clean as possible, and keep the bused

signals (TMS, TCK, TRST and, EMU) as close to the same

length as possible.

Note: The JTAG TAP relies on the state of the TMS line

and the TCK clock signal. If these signals have glitches (due

to ground bounce, crosstalk, etc.) unreliable emulator

operation will result. If you are experiencing emulator

problems, look at these signals using a high-speed digital

oscilloscope. These lines must be clean, and may require

special termination schemes. If you are buffering the JTAG

header (most customers will) you must provide signal ter-

mination appropriate for your target board (series, parallel,

R/C, etc.).

Power Sequence

The power-on sequence for your target and emulation

system is as follows: Apply power to the emulator first, then

to the target board. This ensures that the JTAG signals are

in the correct state for the DSP to run free. Upon power-on,

the emulator drives the TRST signal low, keeping the DSP

TAP in the test-logic-reset state, until the emulation

software takes control. Removal of power should be the

reverse: Turn off power to the target board then to the

emulator.

Emulator Model Specifics

The following sections contain design details on various

emulator pod designs by White Mountain DSP. The

emulator pod is the device that connects directly to the DSP

target board 14-pin JTAG header. Check our web site for

updates to this document that will contain new emulator

design details.

White Mountain DSP JTAG Pod Connector

This section applies to the Mountain ICE, Summit-ICE,

Trek-ICE, Mountain-ICE/WS, Apex-ICE.

Figure 10 details the dimensions of the JTAG pod connector

at the 14-pin target end. Figure 11 displays the keep-out

area for a target board header. The keep-out area allows the

pod connector to properly seat onto the target board header.

This board area should contain no components (chips,

resistors, capacitors, etc.). The dimensions are referenced

to the center of the 0.25” square post pin.

White Mountain DSP 3.3V Pod Logic

This section applies to Mountain ICE, Summit-ICE,

Trek-ICE, Mountain-ICE/WS, Apex-ICE.

A portion of the White Mountain DSP 3.3V emulator pod

interface is shown in Figure 12. This figure describes the

driver circuitry of the emulator pod. As can be seen, TMS,

TCK and TDI are driven with a 33⍀ series resistor. TRST

is driven with a 100⍀ series resistor. TDO and CLKIN are

REV. PrA This information applies to a product under development Its characteristics and specifications are subject to change without notice Analog

17

Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing

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