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ADSP-21992
(Rev.:RevPrA)

Mixed Signal DSP Controller With CAN

Analog Devices 

PRELIMINARY TECHNICAL DATA

August 2002

For current information contact Analog Devices at (781) 937-1799

ADSP-21992

Power Down All Mode

When the ADSP-21992 is in Power Down All mode, the

DSP core clock, the peripheral clock, and the PLL are all

stopped. The DSP does not retain the contents of the

instruction pipeline. The peripheral bus is stopped, so the

peripherals cannot receive data.

To exit Power Down Core/Peripherals mode, the DSP

responds to an interrupt and (after 500 cycles to re-stabilize

the PLL) resumes executing instructions.

core clock is 160 MHz, and the maximum peripheral clock

is 80 MHz—the combination of the input clock and

core/peripheral clock ratios may not exceed these limits.

50MHZ

CLKIN

XTAL

Clock Signals

The ADSP-21992 can be clocked by a crystal oscillator or

a buffered, shaped clock derived from an external clock

oscillator. If a crystal oscillator is used, the crystal should be

connected across the CLKIN and XTAL pins, with two

capacitors connected as shown in Figure 5. Capacitor

values are dependent on crystal type and should be specified

by the crystal manufacturer. A parallel resonant, fundamen-

tal frequency, microprocessor grade crystal should be used

for this configuration.

If a buffered, shaped clock is used, this external clock

connects to the DSP’s CLKIN pin. CLKIN input cannot

be halted, changed, or operated below the specified

frequency during normal operation. This clock signal

should be a TTL compatible signal. When an external clock

is used, the XTAL input must be left unconnected.

The DSP provides a user programmable 1؋ to 32؋ multi-

plication of the input clock, including some fractional

values, to support 128 external to internal (DSP core) clock

ratios. The BYPASS pin, and MSEL6–0 and DF bits, in the

PLL configuration register, decide the PLL multiplication

factor at reset. At runtime, the multiplication factor can be

controlled in software. To support input clocks greater that

100 MHz, the PLL uses an additional bit (DF). If the input

clock is greater than 100 MHz, DF must be set. If the input

clock is less than 100 MHz, DF must be cleared. For clock

multiplier settings, see the ADSP-21992 DSP Hardware

Reference Manual.

The peripheral clock is supplied to the CLKOUT pin.

All on chip peripherals for the ADSP-21992 operate at the

rate set by the peripheral clock. The peripheral clock

(HCLK) is either equal to the core clock rate or one half the

DSP core clock rate (CCLK). This selection is controlled

by the IOSEL bit in the PLLCTL register. The maximum

ADSP-2199X

Figure 5. External Crystal Connections

Reset and Power On Reset (POR)

The RESET pin initiates a complete hardware reset of the

ADSP-21992 when pulled low. The RESET signal must be

asserted when the device is powered up to assure proper

initialization. The ADSP-21992 contains an integrated

power on reset (POR) circuit that provides an output reset

signal, POR, from the ADSP-21992 on power up and if the

power supply voltage falls below the threshold level. The

ADSP-21992 may be reset from an external source using

the RESET signal or alternatively the internal power on

reset circuit may be used by connecting the POR pin to the

RESET pin. During power up the RESET line must be

activated for long enough to allow the DSP core's internal

clock to stabilize. The power up sequence is defined as the

total time required for the crystal oscillator to stabilize after

a valid VDD is applied to the processor and for the internal

phase locked loop (PLL) to lock onto the specific crystal

frequency. A minimum of 2000 cycles will ensure that the

PLL has locked (this does not include the crystal oscillator

start up time).

The RESET input contains some hysteresis. If using an RC

circuit to generate your RESET signal, the circuit should

use an external Schmidt trigger.

The master reset sets all internal stack pointers to the empty

stack condition, masks all interrupts, and resets all registers

to their default values (where applicable). When RESET is

released, if there is no pending bus request, program control

jumps to the location of the on chip boot ROM (0xFF0000)

and the booting sequence is performed.

Power Supplies

The ADSP-21992 has separate power supply connections

for the internal (VDDINT) and external (VDDEXT) power

supplies. The internal supply must meet the 2.5 V require-

ment. The external supply must be connected to a 3.3 V

supply. All external supply pins must be connected to the

same supply.

REV. PrA This information applies to a product under development Its characteristics and specifications are subject to change without notice Analog

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Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing

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