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ADSP-21992
(Rev.:RevPrA)

Mixed Signal DSP Controller With CAN

Analog Devices 

PRELIMINARY TECHNICAL DATA

ADSP-21992

For current information contact Analog Devices at (781) 937-1799

August 2002

The Interrupt Control (ICNTL) register controls interrupt

nesting and enables or disables interrupts globally.

The IRPTL register is used to force and clear interrupts.

On chip stacks preserve the processor status and are auto-

matically maintained during interrupt handling. To support

interrupt, loop, and subroutine nesting, the PC stack is

33 levels deep, the loop stack is eight levels deep, and the

status stack is 16 levels deep. To prevent stack overflow, the

PC stack can generate a stack level interrupt if the PC stack

falls below three locations full or rises above 28

locations full.

The following instructions globally enable or disable

interrupt servicing, regardless of the state of IMASK.

ENA INT;

DIS INT;

At reset, interrupt servicing is disabled.

For quick servicing of interrupts, a secondary set of DAG

and computational registers exist. Switching between the

primary and secondary registers lets programs quickly

service interrupts, while preserving the state of the DSP.

This scheme permits the user to assign the number of

specific interrupts that are unique to their application to the

interrupt scheme of the ADSP-219x core. The user can then

use the existing interrupt priority control scheme to dynam-

ically control the priorities of the 12 core interrupts.

Low Power Operation

The ADSP-21992 has four low power options that signifi-

cantly reduce the power dissipation when the device

operates under standby conditions. To enter any of these

modes, the DSP executes an IDLE instruction. The

ADSP-21992 uses the configuration of the PD, STCK, and

STALL bits in the PLLCTL register to select between the

low power modes as the DSP executes the IDLE instruction.

Depending on the mode, an IDLE shuts off clocks to

different parts of the DSP in the different modes. The low

power modes are:

• Idle

• Power Down Core

• Power Down Core/Peripherals

• Power Down All

Peripheral Interrupt Controller

The Peripheral Interrupt Controller is a dedicated periph-

eral unit of the ADSP-21992 (accessed via IO mapped

registers). The function of the peripheral interrupt control-

ler is to manage the connection of up to 32 peripheral

interrupt requests to the DSP core.

For each peripheral interrupt source, there is a unique 4-bit

code that allows the user to assign the particular peripheral

interrupt to any one of the 12 user assignable interrupts of

the embedded ADSP-219x core. Therefore, the peripheral

interrupt controller of the ADSP-21992 contains 8, 16-bit

Interrupt Priority Registers (Interrupt Priority Register 0

(IPR0) to Interrupt Priority Register 7 (IPR7)).

Each Interrupt Priority Register contains a four 4-bit codes;

one specifically assigned to each peripheral interrupt. The

user may write a value between 0x0 and 0xB to each 4-bit

location in order to effectively connect the particular

interrupt source to the corresponding user assignable

interrupt of the ADSP-219x core.

Writing a value of 0x0 connects the peripheral interrupt to

the USR0 user assignable interrupt of the ADSP-219x core

while writing a value of 0xB connects the peripheral

interrupt to the USR11 user assignable interrupt. The core

interrupt USR0 is the highest priority user interrupt, while

USR11 is the lowest priority. Writing a value between 0xC

and 0xF effectively disables the peripheral interrupt by not

connecting it to any ADSP-219x core interrupt input. The

user may assign more than one peripheral interrupt to any

given ADSP-219x core interrupt. In that case, the onus is

on the user software in the interrupt vector table to

determine the exact interrupt source through reading status

bits etc.

Idle Mode

When the ADSP-21992 is in Idle mode, the DSP core stops

executing instructions, retains the contents of the instruc-

tion pipeline, and waits for an interrupt. The core clock and

peripheral clock continue running.

To enter Idle mode, the DSP can execute the IDLE instruc-

tion anywhere in code. To exit Idle mode, the DSP responds

to an interrupt and (after two cycles of latency) resumes

executing instructions.

Power down Core Mode

When the ADSP-21992 is in Power Down Core mode, the

DSP core clock is off, but the DSP retains the contents of

the pipeline and keeps the PLL running. The peripheral bus

keeps running, letting the peripherals receive data.

To exit Power Down Core mode, the DSP responds to an

interrupt and (after two cycles of latency) resumes executing

instructions.

Power Down Core/Peripherals Mode

When the ADSP-21992 is in Power Down Core/Peripherals

mode, the DSP core clock and peripheral bus clock are off,

but the DSP keeps the PLL running. The DSP does not

retain the contents of the instruction pipeline.The periph-

eral bus is stopped, so the peripherals cannot receive data.

To exit Power Down Core/Peripherals mode, the DSP

responds to an interrupt and (after five to six cycles of

latency) resumes executing instructions.

12 This information applies to a product under development Its characteristics and specifications are subject to change without notice Analog

Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing

REV. PrA

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