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ADF4113HVBCPZ-RL Datasheet PDF : 20 Pages
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Data Sheet
ADF4113HV
SPECIFICATIONS
AVDD = DVDD = 3 V ± 10%, 5 V ± 10%; 13.5 V < VP ≤ 16.5 V; AGND = DGND = CPGND = 0 V; RSET = 4.7 kΩ; dBm referred to 50 Ω;
TA = TMIN to TMAX, unless otherwise noted. Operating temperature range for B version: −40°C to +85°C.
Table 1.
Parameter
B Version
B Chips1
Unit
Test Conditions/Comments
RF CHARACTERISTICS (3 V)
RF Input Sensitivity
−15/0
−15/0
dBm min/max
RF Input Frequency
0.2/3.7
0.2/3.7
GHz min/max For lower frequencies, ensure SR > 130 V/μs
Prescaler Output Frequency2
165
165
MHz max
RF CHARACTERISTICS (5 V)
RF Input Sensitivity
−10/0
−10/0
dBm min/max
RF Input Frequency
0.2/3.7
0.2/3.7
GHz min/max For lower frequencies, ensure SR > 130 V/µs
0.2/4.0
0.2/4.0
GHz min/max Input level = −5 dBm
Prescaler Output Frequency
200
200
MHz max
REFIN CHARACTERISTICS
REFIN Input Frequency
Reference Input Sensitivity
REFIN Input Capacitance
REFIN Input Current
PHASE DETECTOR FREQUENCY
5/150
0.4/AVDD
1.0/AVDD
10
±100
5
5/150
0.4/AVDD
1.0/AVDD
10
±100
5
MHz min/max
V p-p min/max
V p-p min/max
pF max
µA max
MHz max
For f < 5 MHz, ensure SR > 100 V/µs
AVDD = 3.3 V, biased at AVDD/23
For f ≥ 10 MHz, AVDD = 5 V, biased at AVDD/23, 4
CHARGE PUMP
ICP Sink/Source
High Value
RSET = 4.7 kΩ
640
640
μA typ
Low Value
80
80
µA typ
Absolute Accuracy
2.5
2.5
% typ
RSET Range
ICP Three-State Leakage Current
Sink and Source Current Matching
ICP vs. VCP
ICP vs. Temperature
LOGIC INPUTS
3.9/10
5
3
1.5
2
3.9/10
5
3
1.5
2
kΩ typ
nA max
% typ
% typ
% typ
1 V ≤ VCP ≤ VP – 1 V
1 V ≤ VCP ≤ VP – 1 V
VCP = VP/2
VINH, Input High Voltage
VINL, Input Low Voltage
IINH/IINL, Input Current
CIN, Input Capacitance
LOGIC OUTPUTS
0.8 × DVDD
0.2 × DVDD
±1
10
0.8 × DVDD
0.2 × DVDD
±1
10
V min
V max
µA max
pF max
VOH, Output High Voltage
VOL, Output Low Voltage
POWER SUPPLIES
DVDD − 0.4
0.4
DVDD − 0.4
0.4
V min
V max
IOH = 500 µA
IOL = 500 µA
AVDD
DVDD
VP
IDD5 (AIDD + DIDD)
IP
Low Power Sleep Mode
2.7/5.5
AVDD
13.5/16.5
16
0.25
1
2.7/5.5
AVDD
13.5/16.5
11
0.25
1
V min/V max
V min/V max
mA max
mA max
µA typ
11 mA typical
TA = 25°C
NOISE CHARACTERISTICS
Normalized Phase Noise Floor6
−212
−212
dBc/Hz typ
1 The B chip specifications are given as typical values.
2 This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency that
is less than this value.
3 AC coupling ensures AVDD/2 bias.
4 Guaranteed by characterization.
5 TA = 25oC; AVDD = DVDD = 5.5 V; P = 16; RFIN = 900 MHz.
6 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO, PNTOT, and subtracting 20logN (where N is the N divider
value) and 10logfPFD: PNSYNTH = PNTOT − 10logfPFD − 20logN.
Rev. B | Page 3 of 20
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