XWM8706EDS Ver la hoja de datos (PDF) - Wolfson Microelectronics plc
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XWM8706EDS Datasheet PDF : 24 Pages
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WM8706
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I2S MODE
In I2S mode, the MSB is sampled on the second rising edge of BCKIN following a LRCIN
transition. LRCIN is low during the left samples and high during the right samples.
1/fs
LRCIN
LEFT CHANNEL
RIGHT CHANNEL
BCKIN
1 BCKIN
DIN
123
MSB
n-2 n-1 n
LSB
Figure 6 I2S Mode Timing Diagram
1 BCKIN
123
MSB
n-2 n-1 n
LSB
DSP EARLY MODE
In DSP early mode, the first bit is sampled on the BCKIN rising edge following the one which
detects a low to high transition on LRCIN. No BCKIN edges are allowed between the data
words. The word order is DIN left, DIN right.
LRCIN
BCKIN
DIN
1 BCKIN
1/fs
LEFT CHANNEL
RIGHT CHANNEL
12
MSB
n-1 n 1 2
LSB
Input Word Length (IWO)
n-1 n
1 BCKIN
NO VALID DATA
Figure 7 DSP Early Mode Timing Diagram
DSP LATE MODE
In DSP late mode, the first bit is sampled on the BCKIN rising edge which detects a low to high
transition on LRCIN. No BCKIN edges are allowed between the data words. The word order is
DIN left, DIN right.
1/fs
LRCIN
BCKIN
DIN
LEFT CHANNEL
RIGHT CHANNEL
12
MSB
n-1 n 1 2
LSB
Input Word Length (IWO)
n-1 n
NO VALID DATA
1
Figure 8 DSP Late Mode Timing Diagram
WOLFSON MICROELECTRONICS LTD
PP Rev 1.2 April 2001
11
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