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Fabricante

AD6672
(Rev.:Rev0)

IF Receiver

Analog Devices 

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

AD6672

CLK+ 1

CLK– 2

AVDD 3

OR– 4

OR+ 5

0/D0– (LSB) 6

0/D0+ (LSB) 7

DRVDD 8

AD6672

INTERLEAVED

LVDS

TOP VIEW

(Not to Scale)

24 CSB

23 SCLK

22 SDIO

21 DCO+

20 DCO–

19 D9+/D10+ (MSB)

18 D9–/D10– (MSB)

17 DRVDD

Table 8. Pin Function Descriptions

Pin No.

Mnemonic

ADC Power Supplies

8, 17

DRVDD

3, 27, 28, 31, 32

AVDD

0

AGND,

Exposed Paddle

25

ADC Analog

30

29

26

DNC

VIN+

VIN−

VCM

1

2

Digital Outputs

5

4

7

CLK+

CLK−

OR+

OR−

0/D0+ (LSB)

6

0/D0− (LSB)

10

9

12

11

14

13

16

15

19

18

21

20

SPI Control

23

22

24

D1+/D2+

D1−/D2−

D3+/D4+

D3−/D4−

D5+/D6+

D5−/D6−

D7+/D8+

D7−/D8−

D9+/D10+ (MSB)

D9−/D10− (MSB)

DCO+

DCO−

SCLK

SDIO

CSB

NOTES

1. THE EXPOSED THERMAL PADDLE ON THE BOTTOM OF THE

PACKAGE PROVIDES THE ANALOG GROUND FOR THE

PART. THIS EXPOSED PADDLE MUST BE CONNECTED TO

GROUND FOR PROPER OPERATION.

2. DNC = NO NOT CONNECT. DO NOT CONNECT TO THIS PIN.

Figure 3. LFCSP Pin Configuration (Top View)

Type

Description

Supply

Supply

Ground

Digital Output Driver Supply (1.8 V Nominal).

Analog Power Supply (1.8 V Nominal).

Analog Ground. The exposed thermal paddle on the bottom of the package provides the

analog ground for the part. This exposed paddle must be connected to ground for proper

operation.

Do Not Connect. Do not connect to this pin.

Input

Input

Output

Input

Input

Differential Analog Input Pin (+).

Differential Analog Input Pin (−).

Common-Mode Level Bias Output for Analog Inputs. This pin should be decoupled to

ground using a 0.1 μF capacitor.

ADC Clock Input—True.

ADC Clock Input—Complement.

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Overrange indicator—True.

Overrange indicator—Complement.

DDR LVDS Output Data 0—True. The output bit on the rising edge of the data clock output

(DCO) from this output is always a Logic 0 (see Figure 2).

DDR LVDS Output Data 0—Complement. The output bit on the rising edge of the data clock

output (DCO) from this output is always a Logic 0 (see Figure 2).

DDR LVDS Output Data 1/2—True.

DDR LVDS Output Data 1/2—Complement.

DDR LVDS Output Data 3/4—True.

DDR LVDS Output Data 3/4—Complement.

DDR LVDS Output Data 5/6—True.

DDR LVDS Output Data 5/6—Complement.

DDR LVDS Output Data 7/8—True.

DDR LVDS Output Data 7/8—Complement.

DDR LVDS Output Data 9/10—True.

DDR LVDS Output Data 9/10—Complement.

LVDS Data Clock Output—True.

LVDS Data Clock Output—Complement.

Input

Input/output

Input

SPI Serial Clock.

SPI Serial Data I/O.

SPI Chip Select (Active Low).

Rev. 0 | Page 11 of 32

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