AD394 Ver la hoja de datos (PDF) - Analog Devices
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AD394 Datasheet PDF : 12 Pages
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AD394
TIMING
The AD394 control signal timing is very straightforward. CS1–
CS4 must maintain a minimum pulse width of at least 400 ns
for a desired operation to occur. When loading data from a bus
into a 12-bit wide data latch, the data must be stable for at least
210 ns before returning CS to a high state. When CS is low, the
data latch is transparent, allowing the data at the input to propa-
gate through to the DAC. Data can change immediately after the
chip select returns high. DAC settling time is measured from
the falling edge of the active chip select.
Table 5. AD394 Timing Specifications, TMIN to TMAX
Symbol Parameter
Typ
tCS
Chip Select Pulse Width
170
tDA
Data Access Time
0
tDS
Data Setup Time
150
tDH
Data Hold Time
5
Units
ns min
ns min
ns min
ns min
the DAC outputs are accurately developed between the output
pin and Pin 23 (AGND), delivering these signals to remote
loads can be a problem. These problems are compounded if a
current booster stage is used, or if multiple packages are used.
Figure 8 illustrates the parasitic impedances that influence
output accuracy.
Figure 7. Recommended Ground Connections
Figure 6. Timing Diagram
ANALOG CIRCUIT DETAILS
Grounding Rules
The AD394 includes two ground connections to minimize
system accuracy degradation arising from grounding errors.
The two ground pins are designated DGND (Pin 17) and
AGND (Pin 23). The DGND pin is the return for the supply
current and serves as the reference point for the digital input
thresholds. Thus, DGND should be connected to the same
ground as the circuitry that drives the digital inputs.
Pin 23, AGND, is a high quality analog ground connection.
This pin should serve as the reference point for all analog
circuitry associated with the AD394. It is recommended that
any analog signal path carrying significant currents have its
own return connection to Pin 23, as shown in Figure 7.
Several complications arise in practical systems, particularly if
the load is referred to a remote ground. These complications
include dc gain errors due to wiring resistance between DAC
and load, noise due to currents from other circuits flowing in
power ground return impedances, and offsets due to multiple
load currents sharing the same signal ground returns. While
Figure 8. Grounding Errors in Multiple AD394 Systems
An output buffer configured as a subtracter, as shown in
Figure 9, can greatly reduce these errors. First, sensing the
voltage directly at the load with R4 eliminates the effects of
voltage drops in wiring resistance. Second, sensing the remote
ground directly with R3 eliminates the voltage drops caused by
currents flowing through ZGA. Resistors R1 through R4 should
be well matched to achieve maximum rejection of the voltage
appearing across ZGA. Resistors matched to within 1 percent
(including the effects of RW2 and RW3) reduce ground interac-
tion errors by a factor of 100.
Rev. A | Page 8 of 12
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