TTSI2K32T Ver la hoja de datos (PDF) - Agere -> LSI Corporation

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TTSI2K32T

2048-Channel, 32-Highway Time-Slot Interchanger

Agere -> LSI Corporation 

Preliminary Data Sheet

February 1999

TTSI2K32T

2048-Channel, 32-Highway Time-Slot Interchanger

List of Figures

Figures

Page

Figure 1. Block Diagram of the TTSI2K32T .............................................................................................................6

Figure 2. 217-Pin PBGA (Bottom View) ...................................................................................................................7

Figure 3. A Typical TSI Application ........................................................................................................................15

Figure 4. An 8K Time-Slot Switch Made from 4K TSIs ..........................................................................................17

Figure 5. Asynchronous Read................................................................................................................................18

Figure 6. Asynchronous Write................................................................................................................................18

Figure 7. Synchronous Read .................................................................................................................................19

Figure 8. Synchronous Write..................................................................................................................................19

Figure 9. Mixed-Highway Data Rates ....................................................................................................................21

Figure 10. Virtual and Physical Frames .................................................................................................................22

Figure 11. Synchronization to FSYNC ...................................................................................................................23

Figure 12. Highway Offsets ....................................................................................................................................24

Figure 13. Mixed Low-Latency and Frame-Integrity Modes ...................................................................................28

Figure 14. Block Diagram of the TTSI2K32T's Boundary-Scan Test Logic ...........................................................31

Figure 15. BS TAP Controller State Diagram.........................................................................................................32

Figure 16. Asynchronous Read Cycle Timing Using DT Handshake.....................................................................57

Figure 17. Asynchronous Write Cycle Timing Using DT Handshake .....................................................................57

Figure 18. Asynchronous Read Cycle Timing Using Only CS ...............................................................................58

Figure 19. Asynchronous Write Cycle Timing Using Only CS ...............................................................................58

Figure 20. Synchronous Read Cycle Timing..........................................................................................................59

Figure 21. Synchronous Write Cycle Timing ..........................................................................................................59

Figure 22. TDM Highway Timing............................................................................................................................61

Figure 23. JTAG Interface Timing ..........................................................................................................................62

Lucent Technologies Inc.

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