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TTSI2K32T

2048-Channel, 32-Highway Time-Slot Interchanger

Agere -> LSI Corporation 

TTSI2K32T

2048-Channel, 32-Highway Time-Slot Interchanger

Preliminary Data Sheet

February 1999

Contents

Table of Contents

Page

Features .................................................................................................................................................................. 1

Applications ............................................................................................................................................................. 1

Description............................................................................................................................................................... 1

Functional Description ............................................................................................................................................. 5

Pin Information ........................................................................................................................................................ 7

Typical TSI Application .......................................................................................................................................... 15

Interchange Fabric................................................................................................................................................. 16

Small and Large TSIs ............................................................................................................................................ 17

Microprocessor Interface ....................................................................................................................................... 18

Asynchronous Mode (MM = 0)........................................................................................................................... 18

Synchronous Mode (MM = 1) ............................................................................................................................ 19

Highway Data Rate Selection................................................................................................................................ 20

Mixed-Highway Data Rates ................................................................................................................................... 21

TDM Highway Interface Timing ............................................................................................................................. 22

Virtual and Physical Frames .............................................................................................................................. 22

TDM Highway Alignment at Zero Offset ............................................................................................................ 23

TDM Highway Offsets............................................................................................................................................ 23

Reset Sequence .................................................................................................................................................... 24

Low-Latency and Frame-Integrity Modes .............................................................................................................. 25

Low Latency....................................................................................................................................................... 25

Frame Integrity................................................................................................................................................... 26

Test-Pattern Generation ........................................................................................................................................ 29

Test-Pattern Checking........................................................................................................................................... 29

Error Injection ........................................................................................................................................................ 30

Error Checking....................................................................................................................................................... 30

JTAG Boundary-Scan Specification ...................................................................................................................... 31

Principle of the Boundary Scan.......................................................................................................................... 31

Test Access Port Controller ............................................................................................................................... 32

Instruction Register ............................................................................................................................................ 34

Boundary-Scan Register.................................................................................................................................... 35

BYPASS Register .............................................................................................................................................. 35

IDCODE Register............................................................................................................................................... 35

3-State Procedures ............................................................................................................................................ 35

Register Architecture ............................................................................................................................................. 36

Configuration Register Architecture....................................................................................................................... 38

Transmit Highway 3-State Options .................................................................................................................... 51

Data Store Memory ............................................................................................................................................... 52

Connection Store Memory..................................................................................................................................... 52

Absolute Maximum Ratings................................................................................................................................... 55

Operating Conditions............................................................................................................................................. 55

Handling Precautions ............................................................................................................................................ 55

Electrical Characteristics ....................................................................................................................................... 56

Timing Characteristics ........................................................................................................................................... 56

Outline Diagram..................................................................................................................................................... 63

217-Pin PBGA.................................................................................................................................................... 63

Ordering Information.............................................................................................................................................. 64

DS99-045T1E1 Replaces DS97-475TIC to Incorporate the Following Updates ................................................... 64

2

Lucent Technologies Inc.

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