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74LVC3G17DP Ver la hoja de datos (PDF) - NXP Semiconductors.

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74LVC3G17DP Datasheet PDF : 18 Pages
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NXP Semiconductors
74LVC3G17
Triple non-inverting Schmitt trigger with 5 V tolerant input
Table 7. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ[1]
VOH
II
IOFF
ICC
ICC
HIGH-level output voltage
input leakage current
power-off leakage current
supply current
additional supply current
VI = VIH or VIL
IO = 100 µA; VCC = 1.65 V to 5.5 V
IO = 4 mA; VCC = 1.65 V
IO = 8 mA; VCC = 2.3 V
IO = 12 mA; VCC = 2.7 V
IO = 24 mA; VCC = 3.0 V
IO = 32 mA; VCC = 4.5 V
VI = 5.5 V or GND; VCC = 0 V to 5.5 V
VI or VO = 5.5 V; VCC = 0 V
VI = 5.5 V or GND; IO = 0 A;
VCC = 1.65 V to 5.5 V
VI = VCC 0.6 V; IO = 0 A;
VCC = 2.3 V to 5.5 V
VCC 0.1 -
0.95
-
1.7
-
1.9
-
2.0
-
3.4
-
-
-
-
-
-
-
-
-
[1] All typical values are measured at Tamb = 25 °C.
[2] These typical values are measured at VCC = 3.3 V.
Max
-
-
-
-
-
-
±20
±20
40
5
Unit
V
V
V
V
V
V
µA
µA
µA
mA
12. Dynamic characteristics
Table 8. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 9.
Symbol Parameter
Conditions
40 °C to +85 °C
Min
Typ[1]
Max
tpd
propagation delay nA to nY; see Figure 8
[2]
VCC = 1.65 V to 1.95 V
1.5
5.6
10.5
VCC = 2.3 V to 2.7 V
1.0
3.7
6.5
VCC = 2.7 V
1.0
3.8
6.5
VCC = 3.0 V to 3.6 V
1.0
3.6
5.7
VCC = 4.5 V to 5.5 V
1.0
2.7
4.3
CPD
power dissipation per buffer; VCC = 3.3 V;
[3]
-
16.3
-
capacitance
VI = GND to VCC
40 °C to +125 °C Unit
Min
Max
1.5
13.1 ns
1.0
8.5 ns
1.0
8.5 ns
1.0
7.1 ns
1.0
5.4 ns
-
- pF
[1] Typical values are measured at Tamb = 25 °C and VCC = 1.8 V, 2.5 V, 2.7 V, 3.3 V and 5.0 V respectively.
[2] tpd is the same as tPLH and tPHL.
[3] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
Σ(CL × VCC2 × fo) = sum of outputs.
74LVC3G17_6
Product data sheet
Rev. 06 — 6 June 2008
© NXP B.V. 2008. All rights reserved.
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