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AD7302BR

2.7 V to 5.5 V, Parallel Input Dual Voltage Output 8-Bit DAC

Analog Devices 

AD7302

Automatic Update Mode

In this mode of operation the LDAC signal is permanently tied

low. The state of the LDAC is sampled on the rising edge of

WR. LDAC being low allows the selected DAC register to be

automatically updated on the rising edge of WR. The output

update occurs on the rising edge of WR. Figure 23 shows the

timing associated with the automatic update mode of operation

and also the status of the various registers during this frame.

A/B

CS

WR

D7–D0

LDAC = 0

I/P REG (MLE)

HOLD

TRACK

HOLD

DAC REG (SLE)

TRACK

HOLD

TRACK

VOUT

Figure 23. Timing and Register Arrangement for Auto-

matic Update Mode

Simultaneous Update Mode

In this mode of operation the LDAC signal is used to update both

DAC outputs simultaneously. The state of the LDAC is sampled

on the rising edge of WR. If LDAC is high, the automatic update

mode is disabled and both DAC latches are updated at any time

after the write by taking LDAC low. The output update occurs

on the falling edge of LDAC. LDAC must be taken back high

again before the next data transfer takes place. Figure 24

shows the timing associated with the simultaneous update mode

of operation and also the status of the various registers during

this frame.

A/B

CS

WR

D7–D0

LDAC

I/P REG (MLE)

HOLD

TRACK

HOLD

DAC REG (SLE)

HOLD

TRACK

HOLD

VOUT

Figure 24. Timing and Register Arrangement for Simulta-

neous Update Mode

POWER-ON RESET

The AD7302 has a power-on reset circuit designed to allow

output stability during power-up. This circuit holds the DACs

in a reset state until a write takes place to the DAC. In the reset

state all zeros are latched into the input registers of each DAC

and the DAC registers are in transparent mode, thus the output

of both DACs is held at ground potential until a write takes

place to the DAC. The power-on reset circuitry generates a

PON STRB signal, which is a gating signal used within the logic

to identify a power-on condition.

POWER-DOWN FEATURES

The AD7302 has a power-down feature. This is implemented

by exercising the external PD pin; an active low signal puts the

complete DAC into power-down mode. When in power-down

the current consumption of the device is reduced to 1 µA max at

25°C and 2 µA max over temperature, making the device

suitable for use in portable battery powered equipment. When

power-down is activated, the reference bias servo loop and the

output amplifiers with their associated linear circuitry are

powered down, the reference resistors are open circuited to

further reduce the power consumption. The output sees a load

of approximately 23 kΩ to GND when in power-down mode as

shown in Figure 25. The contents of the data registers are

unaffected when in power-down mode. The device comes out

of power-down in typically 13 µs (see Figure 10).

11.7kΩ

IDAC

VREF

11.7kΩ

VDD

Figure 25. Output Stage During Power-Down

Analog Outputs

The AD7302 contains two independent voltage output DACs

with 8-bit resolution and rail-to-rail operation. The output buffer

provides a gain of two at the output. Figures 2 to 4 show the

source and sink capabilities of the output amplifier. The slew

rate of the output amplifier is typically 7.5 V/µs and has a full-

scale settling to 8 bits with a 100 pF capacitive load in typically

1.2 µs.

The input coding to the DAC is straight binary. Table I shows

the binary transfer function for the AD7302. Figure 26 shows

the DAC transfer function for binary coding. Any DAC output

voltage can be expressed as:

where:

VOUT = 2 × VREF (N/256)

␣ ␣ N is the decimal equivalent of the binary input code.

N ranges from 0 to 255.

–10–

REV. 0

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