DatasheetQ Logo
Electronic component search and free download site. Transistors,MosFET ,Diode,Integrated circuits

A3V56S30FTP Ver la hoja de datos (PDF) - Unspecified

Número de pieza
componentes Descripción
Fabricante
A3V56S30FTP Datasheet PDF : 40 Pages
First Prev 11 12 13 14 15 16 17 18 19 20 Next Last
A3V56S30FTP
A3V56S40FTP
256M Single Data Rate Synchronous DRAM
Write operation
Burst write or single write mode is selected
1. Burst write: A burst write operation is enabled by setting OPCODE A9 to 0. A burst write starts in the same clock as a write
command set. (The latency of data input is 0 clock.) The burst length can be set to 1, 2, 4 and 8, like burst read operations.
The write start address is specified by the column address and the bank select address at the write command set cycle.
.
2. Single write: A single write operation is enabled by setting OPCODE A9 to 1. In a single write operation, data is only
written to the column address and the bank select address specified by the write command set cycle without regard to the
burst length setting. (The latency of data input is 0 clock).
Revision 1.1
Page 17 / 39
Mar., 2010

Share Link: 

datasheetq.com  [ Privacy Policy ]Request Datasheet ] [ Contact Us ]