AD5722 Ver la hoja de datos (PDF) - Analog Devices
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AD5722 Datasheet PDF : 31 Pages
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Data Sheet
AD5722/AD5732/AD5752
AC PERFORMANCE CHARACTERISTICS
AVDD = 4.5 V1 to 16.5 V; AVSS = −4.5 V to −16.5 V, or AVSS = 0 V; GND = 0 V; REFIN = 2.5 V; DVCC = 2.7 V to 5.5 V; RLOAD = 2 kΩ;
CLOAD = 200 pF; all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter2
DYNAMIC PERFORMANCE
Output Voltage Settling Time
Slew Rate
Digital-to-Analog Glitch Energy
Glitch Impulse Peak Amplitude
Digital Crosstalk
DAC-to-DAC Crosstalk
Digital Feedthrough
Output Noise
0.1 Hz to 10 Hz Bandwidth
100 kHz Bandwidth
Output Noise Spectral Density
Min Typ Max Unit
Test Conditions/Comments
10 12
7.5 8.5
5
3.5
13
35
10
10
0.6
μs
μs
μs
V/μs
nV-sec
mV
nV-sec
nV-sec
nV-sec
20 V step to ±0.03% FSR
10 V step to ±0.03% FSR
512 LSB step settling (16-bit resolution)
15
μV p-p 0x8000 DAC code
80
μV rms
320
nV/√Hz Measured at 10 kHz, 0x8000 DAC code
1 For specified performance, the maximum headroom requirement is 0.9 V.
2 Guaranteed by design and characterization; not production tested.
TIMING CHARACTERISTICS
AVDD = 4.5 V to 16.5 V; AVSS = −4.5 V to −16.5 V, or AVSS = 0 V; GND = 0 V; REFIN = 2.5 V; DVCC = 2.7 V to 5.5 V; RLOAD = 2 kΩ; CLOAD =
200 pF; all specifications tMIN to tMAX, unless otherwise noted.
Table 3.
Parameter1, 2, 3
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t154
t164
t17
Limit at tMIN, tMAX
33
13
13
13
13
100
7
2
20
130
20
10
20
2.5
13
40
200
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
μs max
ns min
μs max
ns min
ns max
ns min
Description
SCLK cycle time
SCLK high time
SCLK low time
SYNC falling edge to SCLK falling edge setup time
SCLK falling edge to SYNC rising edge
Minimum SYNC high time (write mode)
Data setup time
Data hold time
LDAC falling edge to SYNC falling edge
SYNC rising edge to LDAC falling edge
LDAC pulse width low
DAC output settling time
CLR pulse width low
CLR pulse activation time
SYNC rising edge to SCLK falling edge
SCLK
rising
edge
to
SDO
valid
(CL
5
SDO
=
15
pF)
Minimum SYNC high time (readback/daisy-chain mode)
1 Guaranteed by characterization; not production tested.
2 All input signals are specified with tR = tF = 5 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V.
3 See Figure 2, Figure 3, and Figure 4.
4 Daisy-chain and readback mode.
5 CL SDO = capacitive load on SDO output.
Rev. F | Page 5 of 31
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