UPD63310GK-9EU Ver la hoja de datos (PDF) - NEC => Renesas Technology

Número de pieza

componentes Descripción

Fabricante

UPD63310GK-9EU

STEREO SOUND CODEC

NEC => Renesas Technology 

µPD63310

1.4 Volume Setting Register Addresses

After the power is turned on and a reset has been input, all volume settings are set to mute mode. Therefore, it may

be necessary to specify volume settings before inputting signals. Write data to the volume setting registers that correspond

to the analog input pins and analog output pins to be used.

Since the ADC’s full scale analog input signal amplitude voltage is 1.4 V (TYP.), it may be necessary to specify a

volume setting whereby the signal amplitude’s maximum voltage (after mixing) is no more than 1.4 V, especially when

several analog signals are input to the ADC after mixing.

The addresses of the various volume setting registers are specified via the 6-bit parallel data that is input from the

DATA5 to DATA0 pins during low-level input to the SELR pin. The volume setting registers corresponding to these

addresses are listed below.

0 : IN1L control register

1 : IN1R control register

2 : IN2L control register

3 : IN2R control register

4 : IN3L control register

5 : IN3R control register

6 : IN4L control register

7 : IN4R control register

8 : IN5 control register

9 : IN1L-OUTL control register

10 : IN1R-OUTR control register

11 : IN2L-OUTL control register

12 : IN2R-OUTR control register

13 : IN3L-OUTL control register

14 : IN3R-OUTR control register

15 : IN4L-OUTL control register

16 : IN4R-OUTR control register

17 : DACL-OUTL control register

18 : DACR-OUTR control register

8

Share Link: