PF28F1602C3TD70 Ver la hoja de datos (PDF) - Intel

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Fabricante

PF28F1602C3TD70

Intel® Advanced+ Boot Block Flash Memory (C3)

Intel 

C3 SCSP Flash Memory

Table 13. DC Characteristics

Symbol

Parameter

Device Note

2.7 V – 3.3 V

Min

Max

Units

Test Conditions

VIL

Input Low Voltage

Flash/

SRAM

–0.2

0.6

V

VIH

Input High Voltage

Flash/

SRAM

2.3

VCC

+0.2

V

VOL

Output Low Voltage

Flash/

SRAM

–0.10 0.10

V

F-VCC/S-VCC = VCC Min

IOL = 100 µA

VOH

Output High Voltage

Flash/

SRAM

VCC –

0.1

V

F-VCC/S-VCC = VCC Min

IOH = –100 µA

VPPLK

F-VPP Lock-Out Voltage

Flash

1

1.0

V

Complete Write Protection

VPP1

F-VPP during Program / Erase

Flash

1

1.65

3.3

V

VPP2

Operations

1,2

11.4 12.6

VLKO

VCC Prog/Erase Lock Voltage

Flash

1.5

V

VLKO2

VCCQ Prog/Erase Lock Voltage

Flash

1.2

V

Notes:

1.

Erase and Program are inhibited when F-Vpp < VPPLK and not guaranteed outside the valid F-Vpp ranges of VPP1 and

VPP2.

2.

Applying F-Vpp = 11.4V–12.6V during program/erase can only be done for a maximum of 1000 cycles on the main

blocks and 2500 cycles on the parameter blocks. F-Vpp may be connected to 12 V for a total of 80 hours maximum. See

Section 4.2.1 for details.

Figure 4. Input/Output Reference Waveform

Figure 5.

VCC

INPUT

0.0

VCC

TEST POINTS

2

VCC OUTPUT

2

Note: AC test inputs are driven at VCCQ for a logic “1” and 0.0V for a logic “0.” Input timing begins, and output

timing ends, at VCCQ/2. Input rise and fall times (10%–90%) <10 ns. Worst case speed conditions are

when VCCQ = VCCQMin.

Test Configuration

Device

Under Test

Out

CL

Note: CL includes jig capacitance.

26 Aug 2005

30

Intel® Advanced+ Boot Block Flash Memory (C3) SCSP Family

Order Number: 252636, Revision: 004

Datasheet

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