ST10C167-Q3 Ver la hoja de datos (PDF) - STMicroelectronics
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ST10C167-Q3 Datasheet PDF : 63 Pages
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ST10R167
III - FUNCTIONAL DESCRIPTION
The architecture of the ST10R167 combines
advantages of both RISC and CISC processors
and an advanced peripheral subsystem. The
Figure 3 : Block diagram
block diagram gives an overview of the different
on-chip components and the high bandwidth inter-
nal bus structure of the ST10R167.
32
ROMLESS
CPU-Core
16
16
Internal
RAM
16
2K Byte
16
XRAM
CAN_RXD
CAN_TXD
CAN
PEC
Interrupt Controller
Watchdog
OSC.
XTAL1
XTAL2
16
External
16
Memory
16
8
Port 6
8
Port 5
16
BRG
BRG
Port 3
15
Port 7
8
16
Port 8
8
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