PEB20320 Ver la hoja de datos (PDF) - Infineon Technologies

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Fabricante

PEB20320

Multichannel Network Interface Controller for HDLC

Infineon Technologies 

PEB 20320

Introduction

Pin Definitions and Functions (cont’d)

Pin No.

Symbol

P-MQFP-160-1

40

INT/INT

44

RCLK

45

RSP

46

RDATA

61

SCLK

Input (I) Function

Output (O)

O

Interrupt Request

An interrupt is given when a transmission/

reception error is detected, frames are

received or transmitted, or a host initiated

action is performed. The interrupt pulse

signal interacts with a write cycle to the

shared memory. The data written into the

interrupt queue contains the interrupt

specification.

The interrupt is active high for Intel bus

mode and active low for Motorola bus

mode.

I

Receive Clock

This clock provides the data clock for RDA

T1/DS1 24-channel 1.544 MHz

24-channel 1.536 MHz

CEPT 32-channel 2.048 MHz

32-channel 4.096 MHz

I

Receive Synchronization Pulse

This signal provides the reference for the

receive PCM frame synchronization. It

marks the first bit in the PCM frame.

I

Receive Data

Serial data is received at this PCM input

port. The MUNICH32 supports the T1/

DS1 24-channel PCM format, the CEPT

32-channel PCM format as well as a 32-

channel PCM format with 4.096-Mbit/s bit

rate.

I

System Clock

PCM highway system clock highway

frequency

32-channel 16.384 MHz 2.048 or

4.096 MHz

24-channel 12.288 MHz 1.536 MHz

24-channel 12.352 MHz 1.544 MHz

User’s Manual

19

01.2000

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