MT28F1284W18 Ver la hoja de datos (PDF) - Micron Technology

Número de pieza

componentes Descripción

Fabricante

MT28F1284W18

8 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY

Micron Technology 

8 MEG x 16

ASYNC/PAGE/BURST FLASH MEMORY

WAIT# Signal Polarity

RCR10 sets the WAIT# signal polarity. When

RCR10 = 0, WAIT# is active LOW. When RCR10 = 1, the

WAIT# signal is active HIGH. See “WAIT# Signal Func-

tion” on page 18 for more information.

Hold Data Out

The hold data out (RCR9) specifies for how many

clocks data will be held valid. (See Figure 7.)

Figure 7: Hold Data Output Configuration

CLK

WAIT# (RCR8 = 1)

Hold

Data

1 CLK

WAIT# (RCR8 = 0)

DQ0–DQ15

WAIT# (RCR8 = 0)

Hold

Data

2 CLK

WAIT# (RCR8 = 1)

DQ0–DQ15

NOTE:

1. WAIT# shown active HIGH (RCR10 = 1).

tKHTL

tACLK

VALID

OUTPUT

Note 1

VALID

OUTPUT

Note 1

VALID

OUTPUT

VALID

OUTPUT

tACLK

VALID

OUTPUT

Note 1

Note 1

VALID

OUTPUT

WAIT# Configuration

The wait configuration bit (RCR8) controls the

WAIT# signal behavior for all burst read modes. It

should be set according to the system and CPU charac-

teristics. The WAIT# signal can be configured to assert

either during valid data, or one data cycle before data

becomes valid (see Figure 6). See “WAIT# Signal Func-

tion” on page 18 for more information.

Burst Sequence

The burst sequence (RCR7) specifies the ordering of

data in burst mode. Linear burst order (RCR7 = 1) is the

only burst sequence supported by the device. See

Table 11 for more details.

Clock Configuration

The clock configuration (RCR6) defines the clock

edge on which the burst operation starts and data is

defined.

09005aef80b425b4

MT28F1284W18_D.fm - Rev. D, 11/03 EN

20

Micron Technology, Inc., reserves the right to change products or specifications without notice.

©2003 Micron Technology. Inc.

Share Link: