MT28F1284W18 Ver la hoja de datos (PDF) - Micron Technology
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MT28F1284W18 Datasheet PDF : 66 Pages
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8 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
Status Register
The status register allows the user to determine
whether the state of a PROGRAM/ERASE operation is
pending or complete.
The status register provides the status of the device
to the external microprocessor. During periods when
the WSM is active in a partition, that partition will
default to the read status register mode and can be
polled to determine the WSM status.
After monitoring the status register during a PRO-
GRAM/ERASE operation in a partition, that partition
will remain in read status mode until a new command
is issued to the CSM. Table 7 defines the status register
bits.
Clear Status Register
The internal circuitry can set, but not clear, the
block lock status bit (SR1), the VPP status bit (SR3), the
program status bit (SR4), and the erase status bit (SR5)
of the status register. The CLEAR STATUS REGISTER
command (50h) allows the external microprocessor to
clear these status bits and synchronize to the internal
operations. When the status bits are cleared, the state
of the device does not change.
Table 7: Status Register Bit Definitions
STATUS BIT # STATUS REGISTER BIT
SR7
WRITE STATE MACHINE STATUS
1 = Ready
0 = Busy
SR6
ERASE SUSPEND STATUS
1 = BLOCK ERASE Suspended
0 = BLOCK ERASE in Progress/
Completed
SR5
ERASE STATUS
1 = Error in Block Erasure
0 = Successful BLOCK ERASE
SR4
PROGRAM STATUS
1 = Error in PROGRAM
0 = Successful PROGRAM
SR3
VPP STATUS
1 = VPP Low Detect, Operation Abort
0 = VPP = OK
SR2
PROGRAM SUSPEND STATUS
1 = PROGRAM Suspended
0 = PROGRAM in Progress/Completed
SR1
BLOCK LOCK STATUS
1 = PROGRAM/ERASE Attempted on a
Locked Block; Operation Aborted
0 = No Operation to Locked Blocks
SR0
FAST PROGRAMMING
ALGORITHM STATUS
0 = Partition is busy, but only if SR7 = 0
1 = Another partition is busy, but only
if SR7 = 0
DESCRIPTION
SR7 indicates ERASE or PROGRAM completion in the device.
SR6–SR1 are invalid while SR7 = 0. See Table 8 for valid SR7
and SR0 combinations.
When ERASE SUSPEND is issued, WSM halts execution and
sets both SR7 and SR6 bits to “1.” SR6 bit remains set to “1”
until an ERASE RESUME command is issued.
When this bit is set to “1,” WSM has applied the maximum
number of erase pulses to the block and is still unable to
verify successful block erasure.
When this bit is set to “1,” WSM has attempted but failed to
program a word.
The VPP status bit does not provide continuous indication of
the VPP level. The WSM interrogates the VPP level only after
the PROGRAM or ERASE command sequences have been
entered and informs the system if VPP is LOW. The VPP level
is also checked before the PROGRAM/ERASE is verified by
the WSM.
When PROGRAM SUSPEND is issued, WSM halts execution
and sets both SR7 and SR2 bits to “1.” SR2 bit remains set to
“1” until a PROGRAM RESUME command is issued.
If a PROGRAM or ERASE operation is attempted to a locked
block, SR1 is set by the WSM. The operation specified is
aborted and the device is returned to read status mode.
Addressed partition is erasing or programming. In FPA
mode, SR0 indicates a data stream word has finished
programming or verifying, depending on the FPA phase.
Refer to Table 8 for valid SR7 and SR0 combinations.
09005aef80b425b4
MT28F1284W18_D.fm - Rev. D, 11/03 EN
14
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
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