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MAX7315

8-Port I/O Expander with LED Intensity Control, Interrupt, and Hot-Insertion Protection

Maxim Integrated 

8-Port I/O Expander with LED Intensity

Control, Interrupt, and Hot-Insertion Protection

Table 4. Configuration register (continued)

REGISTER

ADDRESS

CODE

REGISTER DATA

(HEX)

D7

D6

D5

D4

D3

D2

D1

D0

R/W

CONFIGURATION

Disable data change interrupt—INT/O8

—

output is controlled by the O0 and O1 bits

INT

X

O1

O0

I

G

B

E

O

Enable data change interrupt—INT/O8

output is controlled by port input data —

change

X

X

X

X

1

X

X

X

INT/O8 output is low (blink is disabled) —

X

X

X

0

0

X

X

0

INT/O8 output is high impedance (blink is

—

disabled)

X

X

X

1

0

X

X

0

INT/O8 output is low during blink phase 0 —

0x0F

X

X

X

0

0

X

X

1

INT/O8 output is high impedance during

—

blink phase 0

X

X

X

1

0

X

X

1

INT/O8 output is low during blink phase 1 —

INT/O8 output is high impedance during

—

blink phase 1

X

X

0

X

0

X

X

1

X

X

1

X

0

X

X

1

Read-back data change interrupt status

—data change is not detected, and

INT/O8 output is high when interrupt

1

enable (I bit) is set

0

0

X

X

X

X

X

X

Read-back data change interrupt status

—data change is detected, and INT/O8

1

output is low when interrupt enable (I bit)

is set

X = Don’t care.

output port registers, and using the software or hard-

ware controls to flip between the patterns.

If the blink phase 1 register is written with 0xFF, then

the BLINK input can be used as a hardware disable to,

for example, instantly turn off an LED pattern pro-

grammed into the blink phase 0 register. This technique

can be further extended by driving the BLINK input with

a PWM signal to modulate the LED current to provide

fading effects.

The blink mode is enabled by setting the blink enable

flag E in the configuration register (Table 4). When blink

mode is enabled, the state of the blink flip flag sets the

phase, and the output ports are set by either the blink

1

0

X

X

X

X

X

X

phase 0 register or the blink phase 1 register (Table 7).

The blink mode is disabled by clearing the blink enable

flag E in the configuration register (Table 4). When blink

mode is disabled, the blink phase 0 register alone con-

trols the output ports.

Blink Phase Registers

When the blink function is disabled, the blink phase 0

register sets the logic levels of the 8 ports (P0 through

P7) when configured as outputs (Table 8). A duplicate

register called the blink phase 1 register is also used if

the blink function is enabled (Table 9). A logic high sets

the appropriate output port high impedance, while a

logic low makes the port go low.

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