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Fabricante

M50FLW080A

8-Mbit (13 x 64-Kbyte Blocks + 3 × 16 × 4 Kbyte Sectors) 3-V supply, Firmware Hub / low-pin-count Flash memory

STMicroelectronics 

M50FLW080A, M50FLW080B

Bus operations

3.2

3.2.1

3.2.2

3.2.3

3.2.4

Address/Address multiplexed (A/A Mux) bus operations

The Address/Address Multiplexed (A/A Mux) Interface has a more traditional-style interface.

The signals consist of a multiplexed address signals (A0-A10), data signals, (DQ0-DQ7) and

three control signals (RC, G, W). An additional signal, RP, can be used to reset the memory.

The Address/Address Multiplexed (A/A Mux) Interface is included for use by Flash

Programming equipment for faster factory programming. Only a subset of the features

available to the Firmware Hub (FWH)/Low Pin Count (LPC) Interface are available; these

include all the Commands but exclude the Security features and other registers.

The following operations can be performed using the appropriate bus cycles: Bus Read, Bus

Write, Output Disable and Reset.

When the Address/Address Multiplexed (A/A Mux) Interface is selected, all the blocks are

unprotected. It is not possible to protect any blocks through this interface.

Bus Read

Bus Read operations are used to read the contents of the Memory Array, the Electronic

Signature or the Status Register. A valid Bus Read operation begins by latching the Row

Address and Column Address signals into the memory using the Address Inputs, A0-A10,

and the Row/Column Address Select RC. Write Enable (W) and Interface Reset (RP) must

be High, VIH, and Output Enable, G, Low, VIL. The Data Inputs/Outputs will output the value,

according to the timing constraints specified in Figure 16, and Table 28.

Bus Write

Bus Write operations are used to write to the Command Interface. A valid Bus Write

operation begins by latching the Row Address and Column Address signals into the

memory using the Address Inputs, A0-A10, and the Row/Column Address Select RC. The

data should be set up on the Data Inputs/Outputs; Output Enable, G, and Interface Reset,

RP, must be High, VIH; and Write Enable, W, must be Low, VIL. The Data Inputs/Outputs are

latched on the rising edge of Write Enable, W. See Figure 17, and Table 29, for details of the

timing requirements.

Output Disable

The data outputs are high-impedance when the Output Enable, G, is at VIH.

Reset

During the Reset mode, all internal circuits are switched off, the device is deselected, and

the outputs are put at high-impedance. The device is in the Reset mode when RP is Low,

VIL. RP must be held Low, VIL for tPLPH. If RP goes Low, VIL, during a Program or Erase

operation, the operation is aborted, and the affected memory cells no longer contain valid

data. The memory can take up to tPLRH to abort a Program or Erase operation.

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