M50FLW080A Ver la hoja de datos (PDF) - STMicroelectronics

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Fabricante

M50FLW080A

8-Mbit (13 x 64-Kbyte Blocks + 3 × 16 × 4 Kbyte Sectors) 3-V supply, Firmware Hub / low-pin-count Flash memory

STMicroelectronics 

M50FLW080A, M50FLW080B

Signal descriptions

2.1.10

2.1.11

Write Protect (WP)

The Write Protect input is used to prevent the Main Blocks (Blocks 0 to 14) from being

changed. When Write Protect, WP, is driven Low, VIL, Program and Erase operations in the

Main Blocks have no effect, regardless of the state of the Lock Register. When Write

Protect, WP, is driven High, VIH, the protection of the Block or Sector is determined by the

Lock Registers. The state of Write Protect, WP, does not affect the protection of the Top

Block (Block 15). For details, see Appendix A.

Write Protect, WP, must be set prior to a Program or Erase operation is initiated, and must

not be changed until the operation has completed otherwise unpredictable results may

occur. Similarly, unpredictable behavior is possible if WP is changed during Program or

Erase Suspend, and care should be taken to avoid this.

Reserved for Future Use (RFU)

Reserved for Future Use (RFU). These pins do not presently have assigned functions. They

must be left disconnected, except for ID0 and ID1 (when in LPC mode) which can be left

connected. The electrical characteristics for these signals are as described in the

“Identification inputs (ID0-ID3)” section.

2.2

2.2.1

2.2.2

2.2.3

2.2.4

2.2.5

Address/Address multiplexed (A/A Mux) signal descriptions

Please see Figure 2 and Table 2.

Address inputs (A0-A10)

The Address Inputs are used to set the Row Address bits (A0-A10) and the Column

Address bits (A11-A19). They are latched during any bus operation by the Row/Column

Address Select input, RC.

Data inputs/outputs (DQ0-DQ7)

The Data Inputs/Outputs hold the data that is to be written to or read from the memory. They

output the data stored at the selected address during a Bus Read operation. During Bus

Write operations they carry the commands that are sent to the Command Interface of the

internal state machine. The Data Inputs/Outputs, DQ0-DQ7, are latched during a Bus Write

operation.

Output Enable (G)

The Output Enable signal, G, controls the output buffers during a Bus Read operation.

Write Enable (W)

The Write Enable signal, W, controls the Bus Write operation of the Command Interface.

Row/Column Address Select (RC)

The Row/Column Address Select input selects whether the Address Inputs are to be latched

into the Row Address bits (A0-A10) or the Column Address bits (A11-A19). The Row

Address bits are latched on the falling edge of RC whereas the Column Address bits are

latched on its rising edge.

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