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M50FLW080A

8-Mbit (13 x 64-Kbyte Blocks + 3 × 16 × 4 Kbyte Sectors) 3-V supply, Firmware Hub / low-pin-count Flash memory

STMicroelectronics 

M50FLW080A, M50FLW080B

3

Bus operations

Bus operations

The two interfaces, A/A Mux and FWH/LPC, support similar operations, but with different

bus signals and timings. The Firmware Hub/Low Pin Count (FWH/LPC) Interface offers full

functionality, while the Address/Address Multiplexed (A/A Mux) Interface is orientated for

erase and program operations.

See the sections below, The Firmware Hub/low-pin-count (FWH/LPC) bus operations and

Address/Address multiplexed (A/A Mux) bus operations, for details of the bus operations on

each interface.

3.1

3.1.1

Firmware Hub/low-pin-count (FWH/LPC) bus operations

The M50FLW080 automatically identifies the type of FWH/LPC protocol from the first

received nibble (START nibble) and decodes the data that it receives afterwards, according

to the chosen FWH or LPC mode. The Firmware Hub/Low Pin Count (FWH/LPC) Interface

consists of four data signals (FWH0/LAD0-FWH3/LAD3), one control line (FWH4/LFRAME)

and a clock (CLK).

Protection against accidental or malicious data corruption is achieved using two additional

signals (TBL and WP). And two reset signals (RP and INIT) are available to put the memory

into a known state.

The data, control and clock signals are designed to be compatible with PCI electrical

specifications. The interface operates with clock speeds of up to 33MHz.

The following operations can be performed using the appropriate bus cycles: Bus Read, Bus

Write, Standby, Reset and Block Protection.

Bus Read

Bus Read operations are used to read from the memory cells, specific registers in the

Command Interface or Firmware Hub/Low Pin Count Registers. A valid Bus Read operation

starts on the rising edge of the Clock signal when the Input Communication Frame,

FWH4/LFRAME, is Low, VIL, and the correct Start cycle is present on FWH0/LAD0-

FWH3/LAD3. On subsequent clock cycles the Host will send to the memory:

● ID Select, Address and other control bits on FWH0-FWH3 in FWH mode.

● Type+Dir Address and other control bits on LAD0-LAD3 in LPC mode.

The device responds by outputting Sync data until the wait states have elapsed, followed by

Data0-Data3 and Data4-Data7.

See Table 6 and Table 8, and Figure 6 and Figure 8, for a description of the Field definitions

for each clock cycle of the transfer. See Table 26, and Figure 14, for details on the timings of

the signals.

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