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5962F9563501QXC

Radiation Hardened Real Time Express™ Microcontroller

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CONTROL BIT SETTING

TABLE 2. STACK/SUBSTACK CONFIGURATIONS FOR GIVEN CONTROL BIT SETTINGS (Continued)

PARAMETER STACK CONFIGURATION

SVR

SUR

FATAL LIMIT

UNDERFLOW LIMIT

OVERFLOW LIMIT

V15 V14 V13 V12 U10 U9 U8 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

X 0 X X 1 0 X P15 1 1 1 1 1 1 1 P15 0 0 U15 U14 U13 U12 U11 P15 0 V13 V12 V11 V10 V9 V8

X 1 X X 1 0 0 P15 0 1 1 1 1 1 1 P15 1 0 U15 U14 U13 U12 U11 P15 0 V13 V12 V11 V10 V9 V8

X 1 X X 1 0 1 P15 1 1 1 1 1 1 1 P15 0 0 U15 U14 U13 U12 U11 P15 1 V13 V12 V11 V10 V9 V8

0 X X X 1 1 X 1 1 1 1 1 1 1 1 0 0 0 U15 U14 U13 U12 U11 0 V14 V13 V12 V11 V10 V9 V8

1 X X X 1 1 0 0 1 1 1 1 1 1 1 1 0 0 U15 U14 U13 U12 U11 0 V14 V13 V12 V11 V10 V9 V8

1 X X X 1 1 1 1 1 1 1 1 1 1 1 0 0 0 U15 U14 U13 U12 U11 1 V14 V13 V12 V11 V10 V9 V8

NOTES:

18. SPR : Stack Pointer Register, SVR : Stack Overflow Register, SUR : Stack Underflow Register.

19. P0 . . P15: SPR Bits, V0 . . V15: SVR Bits, U0 . . U15: SUR Bits.

20. The Overflow Limit is the stack memory address at which an overflow condition will occur during a stack write operation.

21. The Underflow Limit is the stack memory address below which an underflow condition will occur during a stack read operation.

22. The Fatal Limit is the stack memory address at which a fatal error condition will occur during a stack read or write operation.

23. Stack error conditions remain in effect until a new value is written to the SPR .

24. Stacks and sub-stacks are circular: after writing to the highest location in the stack, the next location to be written to will be the lowest location; after reading the lowest location, the highest

location will be read next.

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