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5962F9563501QXC

Radiation Hardened Real Time Express™ Microcontroller

Intersil 

HS-RTX2010RH

PARAMETER STACK

FATAL ERROR

RETURN STACK FATAL ERROR

SUR

SVR

IBC

151413 12 1110 9 8 7 6 5 4 3 2 1 0

READ-ONLY; FATAL

STACK ERROR FLAG

READ-ONLY; PARAMETER

STACK UNDERFLOW FLAG

READ-ONLY; RETURN

STACK UNDERFLOW FLAG

READ-ONLY; PARAMETER

STACK OVERFLOW FLAG

READ-ONLY; RETURN

STACK OVERFLOW FLAG

DPRSEL: SELECTS

PAGE REGISTER FOR

DATA MEMORY ACCESS

= 1: SELECT DPR

= 0: SELECT CPR

ROUND: MULTIPLIER

CONTROL BIT; SELECTS

ROUNDING OF 16 x 16

BIT MULTIPLICATION

= 1: ROUNDED 16-BIT

PRODUCT

= 0: UNROUNDED

32-BIT PRODUCT

CYCEXT: ALLOWS

EXTENDED CYCLE LENGTH

FOR USER MEMORY

INSTRUCTION CYCLES; SEE

CLOCK AND WAIT

TIMING DIAGRAMS

SELECT TIMER/COUNTER

INPUT SIGNALS: TCLK

OR EI5 - EI3 (TABLE 6)

FIGURE 13. IBC BIT ASSIGNMENTS

IMR : The Interrupt Mask Register has a bit assigned for

each maskable interrupt which can occur. When a bit is set,

the interrupt corresponding to that bit will be masked. Only

the Non-Maskable Interrupt (NMI) cannot be masked. See

Figure 14 for bit assignments for this register.

13

IMR

15 14 13 12 1110 9 8 7 6 5 4 3 2 1 0

RESERVED (NOTE)

EI1

(EXTERNAL INPUT PIN)

PSU, PARAMETER STACK

UNDERFLOW

RSU, RETURN STACK

UNDERFLOW

PSV, PARAMETER STACK

OVERFLOW

RSV, RETURN STACK

OVERFLOW

EI2

TCI 0

TCI 1

TCI 2

EI3

EI4

EI5

SWI

RESERVED (NOTE)

NOTE: Always read as ‘‘0’’. Should be set = 0 during Write operations.

FIGURE 14. IMR BIT ASSIGNMENTS

Stack Controller Registers

SPR : The Stack Pointer Register holds the stack pointer

value for each stack. Bits 0-7 represent the next available

stack memory location for the Parameter Stack, while bits 8-

15 represent the next available stack memory location for the

Return Stack. These stack pointer values must be accessed

together, as SPR . See Figure 15.

SVR : The Stack Overflow Limit Register is a write-only

register which holds the overflow limit values (0 to 255) for

the Parameter Stack (bits 0-7) and the Return Stack (bits

8-15). These values must be written together. See Figure 16.

SUR : The Stack Underflow Limit Register holds the

underflow limit values for the Parameter Stack and the

Return Stack. In addition, this register is utilized to define the

use of substacks for both stacks. These values must be

accessed together. See Figure 17.

SPR

15 14 1312 1110 9 8 7 6 5 4 3 2 1 0

PSP, PARAMETER STACK

POINTER

RSP, RETURN STACK

POINTER

FIGURE 15. SPR BIT ASSIGNMENTS

SVR

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PVL: PARAMETER

STACK OVERFLOW LIMIT.

NUMBER OF WORDS FROM

TOP OF CURRENT SUBSTACK

RVL: RETURN STACK

OVERFLOW LIMIT.

NUMBER OF WORDS FROM

TOP OF CURRENT SUBSTACK

FIGURE 16. SVR BIT ASSIGNMENTS

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