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5962F9563501QXC

Radiation Hardened Real Time Express™ Microcontroller

Intersil 

HS-RTX2010RH

Initialization of Registers

Initialization of the on-chip registers occurs when a HIGH

level on the RTX RESET pin is held for a period of greater

than or equal to four rising edges of ICLK plus 1/2 ICLK

cycle setup and hold times. While the RESET input is HIGH,

the TCLK and PCLK clock outputs are held reset in the LOW

state.

Table 1 shows initialization values and ASIC addresses for

the on-chip registers. As indicated, both the PC and the

CPR are cleared and execution begins at page 0, word 0

when the processor is reset.

The RESET has a Schmitt trigger input, which allows the

use of a simple RC network for generation of a power-on

RESET signal. This helps to minimize the circuit board

space required for the RESET circuit.

To ensure reliable operation even in noisy embedded control

environments, the RESET input is filtered to prevent a reset

caused by a glitch of less than four ICLK cycles duration.

REGISTER

TOP

NEXT

IR

I

CR

MD

SR

PC

IMR

SPR

SUR

IVR

SVR

IPR

DPR

UPR

CPR

IBC

UBR

MXR

TC0 / TP0

TC1 / TP1

TC2 / TP2

MLR

MHR

TABLE 1. REGISTER INITIALIZATION AND ASIC ADDRESS ASSIGNMENTS

HEX

ADDR

INITIALIZED

CONTENTS

DESCRIPTION/COMMENTS

0000 0000 0000 0000 Top Register

1111 1111 1111 1111 Next Register

0000 0000 0000 0000 Instruction Register

00H 01H 1111 1111 1111 1111 Index Register

02H

03H 0100 0000 0000 1000 Configuration Register: Boot = 1; Interrupts Disabled; Byte Order = 0.

04H 1111 1111 1111 1111 Multi-Step Divide Register

06H 0000 0010 0000 0000 Square Root Register

07H 0000 0000 0000 0000 Program Counter Register

08H 0000 0000 0000 0000 Interrupt Mask Register

09H 0000 0000 0000 0000 Stack Pointer Register: The beginning address for each stack is set to a value of ‘0’.

0AH 0000 0111 0000 0111 Stack Underflow Limit Register

0BH 0000 0010 0000 0000 Interrupt Vector Register: Read only; this register holds the current Interrupt Vector

value, and is initialized to the “No Interrupt” value.

0BH 1111 1111 1111 1111 Stack Overflow Limit Register: Write-only; Each stack limit is set to its maximum value.

0CH 0000 0000 0000 0000 Index Page Register

0DH 0000 0000 0000 0000 Data Page Register: The Data Address Page is set for page ‘0’.

0EH 0000 0000 0000 0000 User Page Register: The User Address Page is set for page ‘0’.

0FH 0000 0000 0000 0000 Code Page Register: The Code Address Page is set for page ‘0’.

10H 0000 0000 0000 0000 Interrupt Base/Control Register

11H 0000 0000 0000 0000 User Base Address Register: The User base address is set to ‘0’ within the User page.

12H 0000 0000 0000 0000 MAC Extension Register

13H 0000 0000 0000 0000 Timer/Counter Register 0: Set to time out after 65536 clock periods or events.

14H 0000 0000 0000 0000 Timer/Counter Register 1: Set to time out after 65536 clock periods or events.

15H 0000 0000 0000 0000 Timer/Counter Register 2: Set to time out after 65536 clock periods or events.

16H 0000 0000 0000 0000 Multiplier Lower Product Register

17H 0000 0000 0000 0000 Multiplier High Product Register

15

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