PM25LV020-33QC Ver la hoja de datos (PDF) - PMC-Sierra, Inc

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PM25LV020-33QC

1 Mbit / 2 Mbit / 4 Mbit 3.0 Volt-only, Serial Flash Memory With 33 MHz SPI Bus Interface

PMC-Sierra, Inc 

PMC

Pm25LV010/020/040

DEVICE OPERATION (CONTINUED)

ERASE OPERATION

BLOCK ERASE OPERATION

The memory array of Pm25LV010 is organized into uni-

form 4 Kbyte sectors or 32 Kbyte uniform blocks (sector

group - consists of eight adjacent sectors). The memory

array of Pm25LV020/040 are organized into uniform 4

Kbyte sectors or 64 Kbyte uniform blocks (sector group

- consists of sixteen adjacent sectors). The bottom sec-

tor (Sector 0) of the devices can be configured into four 1

Kbyte smaller sectors.

Before a byte can be reprogrammed, the sector or block

which contains this byte must be erased first. In order to

erase the devices, there are three erase instructions in-

clude Sector Erase (SECTOR_ER), Block Erase

(BLOCK_ER) and Chip Erase (CHIP_ER) instructions

can be used. A sector erase operation allows to erase

any individual sector without affecting the data in others.

A block erase operation allows to erase any individual

block. And a chip erase operation allows to erase the

whole memory array of the devices. Pre-programs the

devices are not required prior to a sector erase, block

erase or chip erase operation.

SECTOR ERASE OPERATION

A SECTOR_ER instruction erases a 4 Kbyte sector or a

1 Kbyte smaller sector (Sector 0_3, Sector 0_2, Sector

0_1, Sector 0_0) if the bottom Sector 0 has been config-

ured as four smaller sectors. Before the execution of

SECTOR_ER instruction, the Write Enable Latch (WEL)

must be enabled through a Write Enable (WREN) instruc-

tion. The WEL will be reset automatically after the

completion of sector erase operation.

The SECTOR_ER instruction is entered, after the CE#

is pulled low to select the device and staying low during

the entire instruction sequence, by shifting in the

SECTOR_ER instruction code and three address bytes

via the SI. Erase operation will start immediately after

the CE# is pulled high, otherwise the SECTOR_ER in-

struction will not be executed. The internal control logic

automatically handles the erase voltage and timing. Re-

fer to Figure 13 for Sector Erase Sequence.

A Block Erase (BLOCK_ER) instruction erases a 32

Kbyte block for the Pm25LV010 or a 64 Kbyte block for

the Pm25LV020/040. Before the execution of

BLOCK_ER instruction, the Write Enable Latch (WEL)

must be enabled through a Write Enable (WREN) instruc-

tion. The WEL will be reset automatically after the

completion of block erase operation.

The BLOCK_ER instruction is entered, after the CE# is

pulled low to select the device and staying low during

the entire instruction sequence, by shifting in the

BLOCK_ER instruction code and three address bytes

via the SI. Erase operation will start immediately after

the CE# is pulled high, otherwise the BLOCK_ER in-

struction will not be executed. The internal control logic

automatically handles the erase voltage and timing. Re-

fer to Figure 14 for Block Erase Sequence.

CHIP ERASE OPERATION

A Chip Erase (CHIP_ER) instruction erases the whole

memory array of Pm25LV010/020/040. Before the ex-

ecution of CHIP_ER instruction, the Write Enable Latch

(WEL) must be enabled through a Write Enable (WREN)

instruction. The WEL will be reset automatically after

the completion of chip erase operation.

The CHIP_ER instruction is entered, after the CE# is

pulled low to select the device and staying low during

the entire instruction sequence, by shifting in the

CHIP_ER instruction code via the SI. Erase operation

will start immediately after the CE# is pulled high, other-

wise the CHIP_ER instruction will not be executed. The

internal control logic automatically handles the erase

voltage and timing. Refer to Figure 15 for Chip Erase

Sequence.

During a erase operation, all instruction will be ignored

except the Read Status Register (RDSR) instruction.

The progress or completion of the erase opertion can be

determined by reading the WIP bit in Status Register

through a RDSR instruction. If WIP bit = “1”, the erase

operation is still in progress. If WIP bit = “0”, the erase

operation has been completed.

Programmable Microelectronics Corp.

19

Issue Date: July, 2005, Rev: 1.2

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