PM25LV020-33QC Ver la hoja de datos (PDF) - PMC-Sierra, Inc

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PM25LV020-33QC

1 Mbit / 2 Mbit / 4 Mbit 3.0 Volt-only, Serial Flash Memory With 33 MHz SPI Bus Interface

PMC-Sierra, Inc 

PMC

Pm25LV010/020/040

DEVICE OPERATION (CONTINUED)

WRITE ENABLE OPERATION

The Write Enable (WREN) instruction is used to set the

Write Enable Latch (WEL) bit. The WEL bit of the

Pm25LV010/020/040 are set as write disable state after

power-up. The WEL bit must be write enabled before

any write operation includes sector, block and

chip erase, page program, write status register, and write

configuration register operations. The WEL bit will be

reset back to write disable state automatically after the

completion of a write operation. The WREN instruction

is required before any above instruction is executed.

Figure 5. Write Enable Sequence

CE#

SCK

SI

INSTRUCTION = 0000 0110b

HI-Z

SO

WRITE DISABLE OPERATION

To protect the device against inadvertent writes, the Write required after the execution of a write instruction. The

Disable (WRDI) instruction resets the WEL bit and dis- WEL will be automatically reset.

ables all write instructions. The WRDI instruction is not

Figure 6. Write Disable Sequence

CE#

SCK

SI

INSTRUCTION = 0000 0100b

HI-Z

SO

Programmable Microelectronics Corp.

13

Issue Date: July, 2005, Rev: 1.2

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