PM25LV020-33QC Ver la hoja de datos (PDF) - PMC-Sierra, Inc

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PM25LV020-33QC

1 Mbit / 2 Mbit / 4 Mbit 3.0 Volt-only, Serial Flash Memory With 33 MHz SPI Bus Interface

PMC-Sierra, Inc 

PMC

Pm25LV010/020/040

DEVICE OPERATION (CONTINUED)

READ CONFIGURATION REGISTER OPERATION

The Read Configuration Register (RDCR) instruction pro- bottom Sector 0 and the write protection setting for each

vides access to the Configuration Register. This instruc- individual 1 Kbyte sector (Sector 0_0 ~ Sector 0_3) within

tion can be used to verify the configuration setting of the Sector 0.

Figure 9. Read Configuration Register Sequence

CE#

SCK

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

SI

INSTRUCTION = 1010 0001b

SO

HIGH IMPEDANCE

DATA OUT

765 43 2 1 0

MSB

WRITE CONFIGURATION REGISTER OPERATION

The Write Configuration Register (WRCR) instruction al-

lows user to enable or disable four smaller 1K byte

sectors and protection for each 1K byte sector by writ-

ing “0”s or “1”s into SCFG and SP0_3 ~SP0_1 in the

congiguration register. please refer table 2 for details.

Do not require WREN command before this WRCR

operation. Because Configuration Register is a data latch

architecture.

Figure 10. Write Configuration Register Sequence

CE#

SCK

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

DATA IN

SI

INSTRUCTION = 1111 0001b

7 65 4 3 2 10

HIGH IMPEDANCE

SO

Programmable Microelectronics Corp.

15

Issue Date: July, 2005, Rev: 1.2

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