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ML6510

Series Programmable Adaptive Clock Manager (PACMan™)

Micro Linear Corporation 

ML6510

FUNCTIONAL DESCRIPTION

Micro Linear’s ML6510 is the first clock chip to use a

feedback mechanism to adaptively (on a real time basis),

eliminate clock skew in high speed personal computer

and workstation system designs. Figure 1 shows a basic

configuration of the ML6510 in a system. The skew

problem results due to the delaying of clock signals in the

system, as shown in Figure 2. Clock skew results from

variation in factors like trace length, PCB trace

characteristics, load capacitance, parasitic capacitance,

temperature and supply variations, etc. Figure 2 shows a

representation of the clock skew problem from a timing

perspective. It shows a worst case example where the

clock signal is delayed so much that its rising edge

completely misses the data it is intended to strobe.

Using a clock deskew mechanism, this problem can be

eliminated and the strobe with the appropriate setup and

hold times with respect to the data bus can be generated.

The ML6510 has eight deskew buffers, each with its own

independent the reflection and error correction circuit.

The deskew buffer eliminates skew by using the reflection

from a remote chip to measure the clock error and then

corrects it by generating the appropriate skew to the clock

output to compensate.

Eight individually deskewed copies of the clock are

provided by the ML6510.

The deskew buffers compensate internally for board-level

skew caused by the PCB trace length variations and

device load variations. This is accomplished by sensing

the round trip delay via a reflected signal, and then

delaying or advancing the clock edge so that all 8 output

clocks arrive at their loads in phase. Each of the eight

clock lines can have any length PCB trace (up to 5ns each

way or 1/4th of the output clock period, whichever is

smaller) and the device loads can vary from line to line.

The ML6510 will automatically compensate for these

variations, keeping the device load clocks in phase.

Although ML6510 will compensate for skew caused by

loading, excessive capacitive loading can cause rise/fall

time degradation at the load. Cascading one ML6510 to

another ML6510 should be done using the PECL reference

clock outputs, to minimize part-to-part skew.

CLOCK REGENERATION

The programmable adaptive clock deskew can function in

a clock regeneration mode to assist in building clock trees

or to expand the number of deskewed clock lines. In this

mode, it has the ability to do clock multiplication or

division as well, while maintaining low skew between

WRITE

SIGNAL

CLOCK

GENERATOR

CPU

DATA

REMOTE

CHIP

CLOCK #0

FEEDBACK #0

CLOCK IN

CLOCK #1

MICRO LINEAR

ML6510

FEEDBACK #1

CLOCK CHIP

CLOCK #7

FEEDBACK #7

Figure 1. Basic System Configuration Using the ML6510.

CLOCK AT

REMOTE CHIP

DATA AT

REMOTE CHIP

DATA

WRITE

SIGNAL

CLOCK AT

REMOTE CHIP

DATA AT

REMOTE CHIP

tS

tH

DATA

Figure 2. The Skew Problem.

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