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Fabricante

ML6510

Series Programmable Adaptive Clock Manager (PACMan™)

Micro Linear Corporation 

ML6510

ELECTRICAL CHARACTERISTICS (Continued)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNIT

AC CHARACTERISTICS rise time, fall time and duty cycle are measured for a generic load; (see Load Conditions section).

tR

Rise time, LOAD [0-7] output

0.8 → 2.0V, 80MHz

150

tF

Fall time, LOAD [0-7] output

2.0 → 0.8V, 80MHz

150

fIN

Input frequency, CLKIN pin

10

fOUT

Output frequency , CLK [0-7]

ML6510-80

10

output

ML6510-130 (Note 2)

10

1500

1500

80

80

130

ps

ps

MHz

MHz

MHz

fVCO

PLL VCO operating frequency

80

DC

Output duty cycle

Measured at device load, at 1.5V

40

160

MHz

60

%

tJITTER

Output jitter

Cycle-to-cycle

Peak-to-peak

75

ps

150

ps

tLOCK

PLL and deskew lock time

After programming is complete

11

ms

SKEW CHARACTERISTICS All skew measurements are made at the load, at 1.5V threshold each output load can vary independently

within the specified range for a generic load (see Load Conditions section).

tSKEWR

Output to output rising

edge skew, all clocks

500

ps

tSKEWF

Output to output

falling edge skew

Output clock frequency ≥ 50MHz

1.5

ns

tSKEWIO

CLKIN input to any

LOAD [0-7] output

rising edge skew

N=M=0

N ≥ 2, M ≥ 2

600

ps

1.25

ns

tRANGE

tSKEWB

Round trip delay CLKX to FBX

pin; output CLK period = tCLK

Output-to-output rising

edge skew, between matched

loads

Output frequency < 50MHz

Output frequency ≥ 50MHz

Providing first (see LOAD

conditions) order matching

order matching between outputs

0

10

ns

0

tCLK/2

250

ps

PART-TO-PART SKEW CHARACTERISTICS Skew measured at the loads, at 1.5V threshold. Reference clock output pins drive clock

input pins of another ML6510.

tPP1

Total load-to-load skew between Slave chip CS = 1, CM = 1 and

multiple chips interfaced with

N = 0, M = 0; RCLK outputs to

reference clock pins.

CLKIN inputs distance less than 2"

tPP2

Total load-to-load skew between Slave chip CS = 1, CM = 1 and

multiple chips interfaced with

N ≥ 2, M ≥ 2; RCLK outputs to

reference clock pins.

CLKIN inputs distance less than 2"

PROGRAMMING TIMING CHARACTERISTICS

1

ns

1

ns

tRESET RESET assertion pulse

width

50

ns

tA1

AUX mode MCLK high time

tA2

AUX mode MCLK low time

tA3

AUX mode MDOUT data

hold time

2000

ns

2000

ns

10

ns

tA4

AUX mode MDOUT data

setup time

10

ns

tA5

AUX mode MCLK period

5000

ns

5

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