ML6510 Ver la hoja de datos (PDF) - Micro Linear Corporation

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Fabricante

ML6510

Series Programmable Adaptive Clock Manager (PACMan™)

Micro Linear Corporation 

ML6510-80

GENERIC

LOAD FBX

R1

CLKX

PCB trace impedance

Z0 = 40Ω to 65Ω

LOAD

Lumped

CL ≤ 20pF

One way trip delay < tRANGE/2

FBX

R1

CLKX

ML6510-80

FIRST-ORDER

MATCHED LOADS

FBY

R1

CLKY

PCB trace impedance

Z0 = 40Ω to 65Ω

Length LX

LOAD Lumped

CLX ≤ 20pF

|CLX – CLY| < 5pF

|LX – LY| < 4"

ZOX = ZOY

PCB trace impedance

Z0 = 40Ω to 65Ω

Length LY

LOAD Lumped

CLY ≤ 20pF

One way trip delay < tRANGE/2

ML6510

ML6510-130

GENERIC

LOAD FBX

R2

CLKX

PCB trace impedance

Z0 = 40Ω to 65Ω

LOAD

Lumped

CL ≤ 20pF

R3

One way trip delay < tRANGE/2

FBX

R2

CLKX

PCB trace impedance

Z0 = 40Ω to 65Ω

LOAD Lumped

CLX ≤ 20pF

ML6510-130

Length LX

R3

FIRST-ORDER

MATCHED LOADS

|CLX – CLY| < 5pF

|LX – LY| < 4"

ZOX = ZOY

FBY

R2

CLKY

PCB trace impedance

Z0 = 40Ω to 65Ω

LOAD Lumped

CLY ≤ 20pF

Length LY

R3

One way trip delay < tRANGE/2

EXTERNAL INPUT CLOCKS

The external input clock to the ML6510 can be either a

differential Pseudo-ECL clock or a single-ended TTL clock.

This is selected using the CS bit in the serial shift register.

For the single-ended TTL clock tie the CLKINH and CLKINL

pins together. The ML6510 ensures that there is a well-

defined phase difference between the input and output

clocks.

RESET AND LOCK

When RESET is de-asserted, the internal programming

logic will become active, loading in the configuration bits

(see Programming the ML6510). Once the configuration is

loaded, the PLL will lock onto the reference signal, and

then the deskew blocks will adapt to the load conditions.

When all eight output clocks are stable and deskewed,

LOCK will be asserted. The asserted polarity of lock is

high. Thus, LOCK can be used to indicate that the system

is ready, or it can be used to drive the RESET input of

another PACMan in a clock tree.

5V

CHIP

VCC

0

RESET

tRESET

LOCK

tLOCK

PROGRAM IN THE

CONFIGURATION

tLOCK

PROGRAM IN THE

CONFIGURATION

RESET may be reasserted at any time to reset the chip

operations. Following a RESET assertion of valid pulse

width (see Programming Electrical Characteristics), the

ML6510 must again be loaded with a configuration, then

it will re-lock and reassert lock when all eight clock

outputs are stable and deskewed.

11

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