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ML6510

Series Programmable Adaptive Clock Manager (PACMan™)

Micro Linear Corporation 

ML6510

PROGRAMMING THE ML6510

The configuration of the ML6510 is programmed by

loading 18 (ML6510-80) or 19 (ML6510-130) bits into the

configuration shift register. To load these bits, the user has

3 options: MAIN, AUX or ROM modes. Which mode is

used is determined by the logic level on the MDIN pin

when RESET is deasserted. If MDIN is tied high, the

ML6510 will assume AUX mode; if its tied low, ROM

mode. If MDIN is high-impedance (i.e. tied to the input of

an EEPROM), it will assume MAIN mode.

1. MAIN Mode

In this mode, the ML6510 will read the configuration bits

from an external serial EEPROM, such as the 93C46, using

the industry standard 3-wire serial I/O protocol. The serial

EEPROM should be a 1K organized in 64 x 16 bits and the

PACMan will read the configuration bits out of the two least

significant 16-bit words. To use this mode, simply connect

the EEPROM serial data input pin to MDIN (ML6510 pin 19),

the EEPROM serial data output pin to MDOUT (ML6510 pin

20), and the EEPROM serial data clock pin to MCLK

(ML6510 pin 21) and CS pin for the EEPROM should be tied

to the RESET signal. After power up, when RESET is

deasserted, the ML6510 will automatically generate the

address and clock to read out the configuration bits. Refer

MAIN Mode waveform in Figure 5.

1K SERIAL

EEPROM

(64 X 16 BIT)

RESET

CS

CLK

DATA IN

DATA OUT

CLOCK

OPCODES

ADDRESS

DATA

ML6510

ROMMSB

MCLK

MDIN

MDOUT

RESET

MAIN Mode Configuration.

2. AUX Mode

When MDIN is tied to VCC, programming the ML6510

will occur via the AUX Mode. This mode shifts the

configuration bits into the shift register directly from the

MDOUT pin. The first 18 (ML6510-80) or 19 (ML6510-

130) clock rising edges provided externally on the MCLK

pin after RESET is deasserted will be used to load the shift

register data, which should be provided on the MDOUT

pin. See figure 6.

µ PROCESSOR

ML6510

ROMMSB

CLOCK

MCLK

VCC

MDIN

DATA

MDOUT

AUX Mode Configuration.

3. ROM Mode

When MDIN is tied to GND, programming the ML6510

will occur via the ROM Mode. This mode reads the

configuration bits directly from an on chip ROM. The

selection of one of the eight preset configuration codes is

accomplished by means of the pins ROMMSB, MCLK and

MDOUT as shown in Tables 1 and 2. The TEST mode

configuration (code 7) is enabled when the TEST bit is set.

In this mode the PLL is bypassed for low frequency testing.

Codes 0-2 are used when the ML6510 clock inputs are

driven from another PACMan’s reference clock outputs.

Code 3 is used when zero phase error is desired between

input and load clocks.

ROM

ADDRESS

BITS

ROMMSB

MCLK

MDOUT

MDIN

ML6510

ROM

8 X 19 BIT

TO SHIFT REGISTER

SERIAL DATA IN

MCLK

(Driven by

ML6510)

MDIN

(Driven by

ML6510)

MDOUT

(Driven by

EEPROM)

tM1

tM2

tM3

01 02 03 04 05 06 07 08 09

SB OP1 OP0 A5 A4 A3 A2 A1 A0

1

1

0

0

0

0

0

0

0

ROM Mode Configuration.

10 11 12 13 • • • 25 26 27 (28)

D15 D14 D13

tM4

•••

D0 D15 D14 (D13)

16 bits data at adddress 0

Figure 5. MAIN Mode Waveforms.

2 bits at address 1

(3 bits for ML6510-130)

12

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