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UT1553B

RTI Remote Terminal Interface

Aeroflex UTMC 

Table 2. Parity Checking

STATE #

EXT TEST

0

0

1

0

2

1

3

1

EXT TST CH SEL A/B

0

1

0

1

Function of TALEN/PARITY

Terminal Address Latch Enable. Active low

signal used to latch TA(4:0) into RTI. Internal

parity checker disabled.

Parity. Internal remote terminal address parity

checker enabled. TALEN/PARITY pin func-

tions as parity bit for TA(4:0) bus. Proper oper-

ation requires odd parity.

Terminal Address Latch Enable. Do not assert

EXT TST during reset, otherwise self-test is

invoked.

Terminal Address Latch Enable. Do not assert

EXT TST during reset, otherwise self-test is

invoked.

The following are examples of sequences used to enter

remote terminal addresses into the RTI.

Example 1.

Hardware-Controlled Remote Terminal

Address (parity check disabled):

STATE 0, 2, or 3 (i.e., 00, 10, or 11)

TALEN - asserted (i.e., logic low)

TA(4:0) - valid RTA

Example 2.

Software-Controlled Remote Terminal

Address (parity check disabled):

EXT TEST and EXT TST CH SEL A/B

in STATE 0, 2, or 3 (i.e., 00, 10, or 11)

CTRL - logic zero

CS - logic zero

RD/WR - logic zero

ADDR IN (0) - logic zero

TALEN - logic one

TA(4:0) - valid RTA

Example 3.

Software Controlled Remote Terminal

Address (parity check enabled):

EXT TEST and EXT TST CH SEL A/B

in STATE 1 (i.e., 01)

CTRL - logic zero

CS - logic zero

RD/WR - logic zero

ADDR IN (0) - logic zero

PARITY - input must provide odd

parity

for the TA(4:0) bus

TA(4:0) - valid RTA

For examples 1 and 2, enabling the parity check circuit

(STATE 1) after the remote terminal address is stored results

in a parity check of the data loaded into the Remote Terminal

Address Register.

1.6 Internal Self-Test

Setting bit 6 of the Control Register to a logic one enables

the internal self-test. Disable Channels A and B at this time

to prevent bus activity during self-test by setting bits 0 and

1 of the Control Register to a logic zero. Normal operation

is inhibited when internal self-test is enabled. The RTI’s

self-test capability is based on the fact that the MIL-STD-

1553B status word sync pulse is identical to the command

word sync pulse. Thus, if the status word from the encoder

is fed back to the decoder, the RTI will recognize the

incoming status word as a command word and thus cause

the RTI to transmit another status word. After the host

invokes self-test, the RTI self-test logic forces a status word

transmission even though the RTI has not received a

command word. The status word is sent to decoder A or B

depending on the channel the host selected for self-test. The

host controls the self-test by periodically changing the bit

patterns in the status word being transmitted. Writing to the

Control Register bits 2, 3, 4, and 8 changes the status word.

Monitor the self-test by sampling either the System Register

or the external status pins (i.e. Command Strobe

(COMSTR), Transmit (XMIT), Receive (RCV)). For a more

detailed explanation of internal self-test, consult the UTMC

publication RTI Internal Self-Test Routine.

1.7 Power-up Master Reset

Reset the RTI by invoking either a hardware or software

master reset after power-up to place the device in a known

state. The master reset clears the decoder and encoder

registers, the command recognition logic, the control and

error logic (which includes the Status, Control and System

Registers), the data transfer logic, and the memory address

control logic. After reset, configure the device for operation

via a Control Register write.

RTI-10

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