UT1553B Ver la hoja de datos (PDF) - Aeroflex UTMC
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UT1553B Datasheet PDF : 52 Pages
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1.4 MIL-STD-1553B Subaddress and Mode Code Definitions
Table 1. Subaddress and Mode Code Definitions Per MIL-STD-1553B
Subaddress Field
Binary (Decimal)
Receive
Message Format
Transmit
Description
00000 (00)
00001 (01)
00010 (02)
00011 (03)
00100 (04)
00101 (05)
00110 (06)
00111 (07)
01000 (08)
01001 (09)
01010 (10)
01011 (11)
01100 (12)
01101 (13)
01110 (14)
01111 (15)
10000 (16)
10001 (17)
10010 (18)
10011 (19)
10100 (20)
10101 (21)
10110 (22)
10111 (23)
11000 (24)
11001 (25)
11010 (26)
11011 (27)
11100 (28)
11101 (29)
11110 (30)
11111 (31)
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Mode Code Indicator
Mode Code Indicator
Note:
1. Refer to mode code assignments per MIL-STD-1553B
1.5 Remote Terminal Address
Assign the RTI remote terminal address by either a software
or hardware exercise. The host assigns the RTI remote
terminal address by performing a Control Register write;
the Terminal Address bus (TA(4:0)) is strobed into the RTI
Remote Terminal Address Register upon completion of the
Control Register write. To assign the RTI remote terminal
address via hardware, use the TALEN/PARITY input pin
operating in the terminal latch address enable mode. The
Terminal Address bus is latched into the RTI while the
TALEN is asserted (i.e., logic low). Valid remote terminal
addresses (RTA) include decimal 0 through 31 if Broadcast
is disabled, 0 through 30 if Broadcast is enabled
Parity Checker
An address parity check is performed to insure the remote
terminal address applied to TA(4:0) was properly latched
into the Remote Terminal Address Register. To perform a
parity check, enable the RTI parity circuit via EXT TEST
and EXT TST CH SEL A/B input pins. The parity bit is
entered through the TALEN/PARITY input pin operating in
the parity mode. Input pins EXT TEST and EXT TST CH
SEL A/B control dual-function input pin TALEN/PARITY;
see table 2 for description of operation.
If a parity error exists, the Parity Error bit of the System
Register is set to a logic one, biphase Channels A and B are
disabled (set to logic zero), the Message Error bit set to logic
one, and the message error pin is asserted.
RTI-9
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