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A8251

Programmable Communications Interface

Altera Corporation 

a8251 Programmable Communications Interface Data Sheet

Figure 8. Transmitter Control Signals (Synchronous)

The X indicates “don’t care.”

ncts

txempty

txrdy

(Status Bit)

txrdy

(Pin)

cnd

X

X

X

X

X

nwr

Sync Characters Data Characters Sync Characters

One Two One Two One Two

txd

Parity Bit

Parity Bit

Parity Bit

The txrdy and txempty signals function identically when programmed

for asynchronous or synchronous operation. However, when the

transmitter becomes empty, the a8251 automatically inserts sync

characters into the data stream. If the scs signal is high, a single sync

character is inserted. Otherwise, two sync characters are inserted.

Reset Operation

The a8251 is reset in one of two ways:

s Total state reset

s Internal state reset

Total state reset is an asynchronous operation achieved by asserting the

reset input. All internal registers and control logic are asynchronously

reset to their initial state.

Internal state reset is achieved by writing a logic high into bit 6 (ir) of the

command instruction register, which resets all internal registers and

control logic to their initial state. Internal state reset occurs synchronously

to the rising edge of the clk signal. The master clock signal (clk) must be

running to achieve an internal state reset.

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Altera Corporation

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