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A8251

Programmable Communications Interface

Altera Corporation 

a8251 Programmable Communications Interface Data Sheet

Figure 5. Transmitter Control & Error Signals (Asynchronous)

The X indicates “don’t care.”

ncts

txempty

txrdy

(Status Bit)

txrdy

(Pin)

cnd X

X

X

X

X

X

nwr

txd

First

Data Bit

Second

Data Bit

Third

Data Bit

Transmitter Start Bit

When data is transferred to the shift register, a start bit (i.e., logic low) is

placed on the txd signal on the falling edge of the ntxc signal. The start

bit value remains active for the number of clock cycles specified by the

divide-by mode (i.e., 1, 16, or 64). See Figure 6.

Figure 6. Transmitter Data & Clock Signals

ntxc (Divide-by-1)

ntxc (Divide-by-16)

txd

Start Bit

Data Bit

Transmitter Data

After the start bit is transmitted, the data bits shift out of the TBR one at a

time, from the least significant to the most significant. The cycle time for

each bit starts at the beginning of the clock cycle, which depends on the

specified divide-by mode. The number of bits shifted out corresponds to

the number of bits specified in the MIR.

Altera Corporation

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