A8251 Ver la hoja de datos (PDF) - Altera Corporation

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A8251

Programmable Communications Interface

Altera Corporation 

a8251 Programmable Communications Interface Data Sheet

Synchronization may occur either externally or internally. When external

sync detect is selected, the synchronization process is as follows:

1. The microprocessor issues an enter hunt (eh) command to the

command instruction register.

2. The external sync detect circuitry forces the extsyncd signal high

for at least one nrxc cycle. The extsyncd is sampled on the falling

edge of nrxc, which forces the a8251 to stop looking for sync

characters. At this point, the a8251 begins sampling rxd on the next

rising edge of nrxc.

The syn_brk signal and corresponding status bit are asserted and

automatically cleared when the microprocessor reads the status data.

When internal sync detect is selected, the receiver is responsible for

detecting sync characters on the rxd signal. The sequence is as follows:

1. The microprocessor issues an enter hunt (eh) command to the

command instruction register.

2. The receiver section begins sampling for rxd on the rising edge of

nrxc. The rxd input data is compared to the sync character(s).

3. Upon detecting the sync character(s), the a8251 begins sampling for

the rxd signal on the next rising edge of nrxc.

The syn_brk output and the corresponding status bit are asserted and

automatically cleared when the microprocessor reads the status data.

Parity and overrun errors are detected as in asynchronous operation.

Synchronous operation continues until the microprocessor issues another

enter hunt (eh) command.

Transmitter Operation (Synchronous)

A transmitter operation starts when the microprocessor writes the first

character (usually a sync character) to the TBR. Once the ncts signal is

asserted, the a8251 begins shifting the data byte out on the falling edge

of the ntxc signal. Data transmission is synchronous to the ntxc clock.

As in asynchronous operation, a parity bit is added to each data byte to

determine the parity. See Figure 8.

Altera Corporation

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