Q67100-H5095 Ver la hoja de datos (PDF) - Infineon Technologies

Número de pieza

componentes Descripción

Fabricante

Q67100-H5095

Nonvolatile memory 2-Kbit E2PROM with I2C bus

Infineon Technologies 

SDA 2526-5

Figure 2

Timing Conditions for the I2C Bus (high-speed mode)

Parameter

Symbol

Limit Values

Unit

min.

max.

Minimum time the bus must be free

before a new transmission can start

Start condition hold time

Clock low period

Clock high period

Start condition set-up time,

only valid for repeated start code

Data set-up time

Rise time of both the SDA- and SCL-line

Fall time of both the SDA- and SCL-line

Stop condition set-up time

Hold time data

tBUF

4.7

µs

tHD;STA 4.0

µs

tLOW

4.7

µs

tHIGH

4.0

µs

tSU;STA 4.7

µs

tSU;DAT 250

ns

tR

1

µs

tF

300

ns

tSU;STO 4.7

µs

tHD;DAT 0*)

* Note that a transmitter must internally provide at least a hold time to bridge the undefined region (max. 300 ns)

of the falling edge of SCL.

Semiconductor Group

26

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