STV5730A Ver la hoja de datos (PDF) - STMicroelectronics
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STV5730A Datasheet PDF : 20 Pages
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STV5730A
FUNCTIONAL DESCRIPTION (continued)
2 - THE MICROPROCESSOR SERIAL INTERFACE
The STV5730A is down loaded by the microprocessor through a three wire serial interface : DATA, CLK,
CSN. The CLK and CSN signals are internally ORed in order to validate the transfer when the STV5730A
is chip selected only (i.e. CSN = 0). The CSN rising edge validates the internal data transfer.
2.1 - Message Formats (see Figure 2)
16-bit, 8-bit and 0-bit formats are available. The 8-bit and 0-bit message formats may be useful to speed
up the STV5730A down loading.
15
12 11
87654
0000
BUF[11:8]
STRU[7:6] 0
DEPL[4:0]
0
ADDRESS
This 16-bit address message loads the serial interface write pointer. This address is incremented after each
data message.
15
12 11
0
0001
DATA[11:0]
This 16-bit data message writes the data at the location indicated by the write pointer.
DATA
7
0
DATA[7:0]
DATA
This 8-bit data message writes the data at the location indicated by the write pointer. The 4-bit data MSB
is copied from the last previous 16-bit data message.
The 0-bit data message writes a data at the location indicated by the write pointer. The last data is used
from the previous 8-bit or 16-bit data message.
15
00
12 11
10
don’t care
0
CONTROL
This 16-bit control message stops the 4*fsc quartz oscillator.
15
00
12 11
11
don’t care
0
CONTROL
This 16-bit control message resets the circuit and starts the 4*fsc quartz oscillator. This message should
not be used if an external 4 x fsc clock is used instead of the quartz. It is mandatory that reset operation is
as described in paragraph 2.3.
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