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22051AKHC

Multistandard Digital Video Decoder Three-Line Adaptive Comb Decoder Family, 8 & 10 bit

Fairchild Semiconductor 

PRODUCT SPECIFICATION

TMC22x5yA

Control Register Definitions

Global Control Register (00)

7

6

5

4

3

2

1

0

SRST

HRST

SET

DHVEN

STD

Reg Bit

00

7

Name

SRST

00

6

HRST

00

5-3 SET

Description

Software reset. When LOW, resets and holds internal state machines and

disables outputs. When HIGH (normal), starts and runs state machines and

enables outputs. This bit is ignored while HRST is high.

Hardware reset. When HRST is HIGH, SRST is forced low when RESET pin

is taken LOW. State machines are reset and held. When HRST is low the

RESET pin can be taken HIGH at any time. The state machines remain

disabled until SRST is programmed HIGH. When HRST is high the state

machines are enabled as soon as the RESET pin goes HIGH.

SET pin function. These bits control the set function when the SET pin goes

low.

A = all outputs high-impedance

B = internal state machines

C = burst locked loop

SET Function

000 Reset and hold A, B, & C.

001 Set output to BLUE and flywheel B & C. (RGB outputs)

Set output to "color" and flywheel B & C (YCBCR outputs)

010 Hold A, lock B & C to external input

011 Reset C only

100 Reset B & C

101 Set output to BLUE and lock B & C to input video (RGB output)

110 Line and pixel grab depending on VMCR6-0 (reg 30)

111 Toggle reset function of SET = 010. For each SET = 0 pulse the

chip operation will change from normal to that of SET = 010 or

visa versa.

00

2

DHVEN

00

1-0 STD

The first SET pulse after a software or hardware reset, with SET = 111,

causes a toggle to SET = 010.

Output H&V sync enable. Disables DHSYNC and DVSYNC signals when

HIGH.

Selects video standard. Selects video standard.

SET Function

00

NTSC

01

reserved

10

PAL/M

11

All PAL standards except PAL/M

REV. 1.0.0 2/4/03

11

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