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MFC2000

Multifunctional Peripheral Controller 2000

Conexant Systems 

Table 8-6. PADC Timing Diagram ......................................................................................................................................... 8-4

Table 8-7. TADC Block Diagram ........................................................................................................................................... 8-5

Table 9-1. Untitled Table ....................................................................................................................................................... 9-2

Table 9-2: Procedure to determine Pixels to remove........................................................................................................... 9-17

Table 9-3: Resolution Conversion Examples....................................................................................................................... 9-17

Table 12-1. Full Step/Single Phase Excitation..................................................................................................................... 12-3

Table 12-2. Full Step/Two Phase Excitation ........................................................................................................................ 12-3

Table 12-3. Half-Step Excitation .......................................................................................................................................... 12-3

Table 12-4. Full Step/Single Phase Excitation..................................................................................................................... 12-7

Table 12-5. Full Step/Two Phase Excitation ........................................................................................................................ 12-7

Table 12-6. Half-Step Excitation .......................................................................................................................................... 12-8

Table 18-1. RTC Crystal Specifications for 32.768 kHz....................................................................................................... 18-4

Table 20-1. Bell/Ringer Setting............................................................................................................................................ 20-2

Table 23-1. SSD Registers .................................................................................................................................................. 23-4

Table 23-2. P80 CORE Registers........................................................................................................................................ 23-5

Table 24-1. Needs a title.................................................................................................................................................... 24-11

Table 24-2. DMA Channels: Functionality and Priorities ................................................................................................... 24-12

Table 24-3. DMA Parameters Scratch Pad Addresses...................................................................................................... 24-13

Table 24-4: Supported FPDRAM Chip Characteristics...................................................................................................... 24-23

Table 24-5: Supported SDRAM Chip Characteristics ........................................................................................................ 24-23

Table 24-6. Untitled table................................................................................................................................................... 24-25

Table 24-7. Untitled table................................................................................................................................................... 24-26

Table 24-8. Untitled table................................................................................................................................................... 24-26

Table 24-9. SDRAM Setup and Hold Timing ..................................................................................................................... 24-29

Table 24-10. Timing Parameters for 16-bit SDRAM Read and Write ................................................................................ 24-31

Table 24-11. Timing Parameters for 8-bit SDRAM Read and Write .................................................................................. 24-31

Table 24-12. 60ns Timing .................................................................................................................................................. 24-32

Table 24-13. 50ns Timing .................................................................................................................................................. 24-32

Table 24-14. FPDRAM Timing (Refresh)........................................................................................................................... 24-33

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