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SP8121 Ver la hoja de datos (PDF) - Signal Processing Technologies

Número de pieza
componentes Descripción
Fabricante
SP8121
Sipex
Signal Processing Technologies Sipex
SP8121 Datasheet PDF : 13 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
ABSOLUTE MAXIMUM RATINGS
VCC to Common Ground .............................................. 0V to +16.5V
VLOGIC to Common Ground ............................................... 0V to +7V
Analog Common to Digital Common Ground ............... -0.5V to +1V
Digital Inputs to Common Ground .................... -0.5V to VLOGIC+0.5V
Digital Outputs to Common Ground ................. -0.5V to VLOGIC+0.5V
Multiplexer Analog Inputs ...................................... -16.5V to +31.5V
Gain and Offset Adjustment ................................ -0.5V to VCC+0.5V
Analog Input Maximum Current ........................................... 100mA
Temperature with Bias Applied ............................. -55°C to +125°C
Storage Temperature ............................................ -65°C to +150°C
Lead Temperature, Soldering .................................... 300°C, 10sec
CAUTION:
ESD (ElectroStatic Discharge) sensitive
device. Permanent damage may occur on
unconnected devices subject to high energy
electrostatic fields. Unused devices must be
stored in conductive foam or shunts.
Personnel should be properly grounded prior
to handling this device. The protective foam
should be discharged to the destination
socket before devices are removed.
SPECIFICATIONS
(TA= 25°C and nominal supply voltages unless otherwise noted)
MIN. TYP. MAX.
ANALOG INPUTS
Input Voltage Range
Multiplexer Inputs
Configuration
Input Impedance
ON Channel
OFF Channel
Input Bias Current/Channel
Crosstalk
OFF to ON Channel
0 to +5
8
Single-ended
109
1010
+10
+250
-90
-80
-70
ACCURACY
Resolution
Linearity Error
–K
–J
Differential Non-Linearity
–K
–J
Offset Error
Gain Error
No Missing Codes
–K
12
+0.5
+1
+1
+2
+0.5
+4
+0.3
+1
Guaranteed
TRANSFER CHARACTERISTICS
Throughput Rate
100
MUX Settling/Acquisition
1.9
A/D Conversion
8.1
STABILITY
Linearity
Offset
Gain
+0.5 +2.5
+5
+25
+10
+50
DIGITAL INPUTS
Capacitance
Logic Levels
VIH
VIL
IIH
IIL
5
+2.4
+5.5
-0.5
+0.8
+5
+5
UNIT
V
CONDITIONS
nA
nA
dB
dB
dB
Bits
LSB
LSB
LSB
LSB
LSB
%FSR
Parallel with 30pF
Parallel with 5pF
25°C
-55°C to +125°C
10kHz, 0V to +5VPk-to-pk
50kHz, 0V to +5VPk-to-pk
100kHz, 0V to +5VPk-to-pk
Adjustable to zero
Adjustable to zero
kHz
µs
µs
ppm/°C
ppm/°C
ppm/°C
pF
V
V
µA
µA
SP8121DS/02
SP8121 Monolithic, 12-Bit Data Acquisition System
2
© Copyright 2000 Sipex Corporation

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