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AD1803 Ver la hoja de datos (PDF) - Analog Devices

Número de pieza
componentes Descripción
Fabricante
AD1803
ADI
Analog Devices ADI
AD1803 Datasheet PDF : 32 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
AD1803
Parameter
MONITOR OUTPUT
Digital-to-Analog Converter
Dynamic Range2, 5
THD + N2, 5
Test Conditions/Comments
−60 dB input, A-weighted
Programmable Gain/Attenuator
Step Size2
Output Attenuation Span2
DIGITAL DECIMATION AND INTERPOLATION
FILTERS2
Pass-Band Edge
Pass-Band
Pass-Band Ripple
Transition Band
Stop-Band Edge6
Stop-Band Rejection
Group Delay
Group Delay Variation Over Pass Band
0 kHz to 4 kHz
0 kHz to 8 kHz
Sample Rate
STATIC DIGITAL
VIH, High Level Input Voltage
VIL, Low Level Input Voltage
VOH, High Level Output Voltage
VOL, Low Level Output Voltage
Input Leakage Current
Output Leakage Current
POWER SUPPLY
AVDD Range
DVDD Range
Analog and Digital Supply Current
Analog and Digital Supply Current
Power Supply Rejection7
CLOCK
Input Clock Frequency
Recommended Clock Duty Cycle
−18 dB to +45 dB
−0.22 dB point
−3.0 dB point
Plus 3 dB roll-off
Digital Inputs
IOH = −0.5 mA
IOL = +0.5 mA
3.3 V/5 V
3.3 V/5 V
5 V, see Table 2
3.3 V, see Table 2
100 mV p-p, signal @ 1 kHz
Min
Typ
Max
Unit
50
0.316
−50
dB
1
%
−40
dB
2.4
3.0
3.6
dB
63
dB
0.0
0.445 × fS
0.555 × fS
78.0
6.4
0.445 × fS Hz
0.490 × fS Hz
−0.2
dB
0.555 × fS Hz
Hz
dB
21/fS
s
0.45
μs
1.30
μs
16
kHz
0.65 × DVDD
V
0.35 × DVDD
V
0.9 × DVDD
V
0.1 × DVDD
V
−10
+10
μA
−10
+10
μA
3.0/4.75
3.0/4.75
3.6/5.25 V
3.6/5.25 V
12.288
45
40
24.576
50
dB
32.768 MHz
55
%
1 RMS values assume sine wave input.
2 Guaranteed by design, not production tested.
3 All steps tested.
4 The ADC gain is achieved using a 0 dB to 22.5 dB variable gain stage and a 20 dB fixed gain stage. The 22.5 dB to 42.5 dB gain steps are achieved by enabling the 20 dB gain stage.
5 THD + N referenced to full scale.
6 The stop band repeats itself at multiples of 64 × fS, where fS is the sampling frequency. The digital filter attenuates to −78.0 dB or better across the frequency spectrum,
except for a range ±0.555 × fS wide at multiples of 64 × fS.
7 At both analog and digital supply pins (both ADCs and DACs).
Rev. A | Page 4 of 32

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