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MAS281L

MIL-STD-1750A Microprocessor

Dynex Semiconductor 

MAS281

2.2 PIN FUNCTIONS

2.2.3 SYNCHRONIZATION CLOCK (SYNC)

A description of each pin function follows. The function

name is presented first, followed by its acronym and

description. Function type is either input, output, high

impedance (Hi-Z), or a combination thereof. Full timing

characteristics of each of the functions are shown in section

6.0.

2.2.1 POWER AND GROUND (VDD & GND)

The MAS281 utilizes a single VDD power supply. A

singlepoint ground is provided for the three chips on the

substrate and is brought out on two module pins.

2.2.2 OSCILLATOR (OSC)

This input clocks the EU state sequencer which, in turn,

generates timing and control signals for the rest of the module.

To minimize skew between OSC edges and signals derived

from OSC, and thereby optimize system performance, the

OSC rise and fall times should be minimised. It is

recommended that a clock driver with a high drive capability,

such as a 54AS244, 54ALS244 or 54HST244, be used.

This active low output transitions from high to low to signal

the start of a new machine cycle. It should be used as a timing

reference for those operations which must be synchronized to

the basic machine cycle.

SYNCN cycles associated with external memory or l/O bus

transactions are a minimum of five OSC periods in duration

and may be extended by inserting wait states via the external

ready interface, For such cycles, a SYNCN low indicates that

either an address or XlO command is on the AD bus; a high

indicates data is on the bus. Wait states extend the high state

of SYNCN.

SYNCN cycles associated with internal CPU operations,

are either five or six OSC periods in duration. Six OSC periods

are required for machine cycles associated with microcode

branches or with the execution of internally decoded XlO

commands. Five OSC periods are required for all other internal

operations.

[Note: For modules operating at high OSC frequencies, the

internal ready logic provided on the IU may cause a wait state

to be inserted during execution of internal XlO commands.

This would result in a SYNCN cycle of seven OSC periods

duration. Though unlikely, this condition must be taken into

account in implementing an external ready interface. Refer to

the description of the Ready (RDYN) signal below for further

details.]

SYNCN continues to cycle during DMA and HOLD states.

Such cycles are five OSC periods in duration.

2.2.4 ADDRESS STROBE (AS)

AD11

Output/Hi-Z. This active high signal indicates that an

address has been placed on the AD bus. This address is

guaranteed valid at the high to low transition of AS. AS should

be used to strobe an address latch during AD bus

demultiplexing. This latch should be a transparent type for

optimum performance. AS is placed in the high impedance

state during DMA and Hold cycles and is held low during

internal (non-XIO) operations.

2.2.5 DATA STROBE (DS)

Output/Hi-Z. This active low signal indicates that the AD

bus is being used for data transfers. During read operations,

DSN should be used by the selected external device to enable

data onto the AD bus. This data is guaranteed valid on the low

to high transition of DSN. The selected external device should

use the low to high edge of DSN to perform the write. DSN is

placed in the high impedance state during DMA and Hold

cycles and is held high during internal (nonXlO) operations.

Figure 4: Pin Assignments

2.2.6 READ/WRITE (RD/W)

Output/Hi-Z, This dual function signal indicates the

direction of data flow on the AD bus. A high level indicates a

read operation with data being input to the module. A low level

indicates a write operation with data being output by the

module. RD/WN may be combined with DSN to generate

separate read and write strobes. This signal goes valid shortly

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