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MAQ281C

MIL-STD-1750A Microprocessor

Dynex Semiconductor 

MAS281

1.0 ARCHITECTURE

The MAS281 Microprocessor is a high performance

implementation of the MIL-STD-1750A (Notice 1) instruction

set architecture. It consists of three custom CMOS/SOS Large

Scale Integration chips referred to as the Execution Unit,

Control Unit, and Interrupt Unit - mounted on, and

interconnected within, a 64-pin, dual in-line ceramic substrate.

Figure 1 depicts the interconnection of these chips via the

substrate while Figure 2 depicts the architectural details within

each chip.

Unit (MMU), this address space may be expanded to a full

1Mword. Furthermore, this configuration provides write and

access lock and key protection down to 4K-word blocks. By

also configuring the MA31751 as a Block Protect Unit (BPU),

write protection may be extended down to 1K-word blocks. For

those applications not requiring adherence to the address

space requirements of MIL-STD-1750A, the MAS281 may be

optionally configured with up to 1Mword each of instruction

and operand space.

In addition to implementing all of the required features of

MIL-STD-1750A, the MAS281 also incorporates a number of

optional features. Interval timers A and B as well as a trigger-

go counter are provided. Most specified XIO commands are

decoded directly on the module and an additional set of

commands, associated with MMU and BPU operations, are

directly decoded on the MA31751 chip. Those commands not

directly decoded are output for decoding by external logic in

accordance with the XIO and VIO protocols of MIL-STD-

1750A.

1.1 EXECUTION UNIT (EU)

The EU provides the computational resources for the

MAS281. Key features include: (1) a three-bus (R, S, and Y)

data path consisting of an arithmetic/logic unit (ALU), three-

port register file, barrel shifter, parallel multiplier/accumulator,

and status register; (2) instruction fetch registers IC, IA, and IB;

(3) operand transfer registers A, Dl, and DO; (4) a state

sequencer; and (5) microinstruction decode logic. A brief

description of these features follows:

1.1.1 ARITHMETIC/LOGIC UNIT (ALU)

Figure 1: MAS281 Microprocessor Block Diagram

A full function 16-bit ALU is used to perform arithmetic and

logic operations on one or two 16-bit operands in a single

machine cycle. The ALU supports 16-bit fixed-point single-

precision, 32-bit fixed-point double-precision, 32-bit floating-

point, and 48-bit floating-point extended precision data in two’s

complement form. The ALU generates several machine flags

which reflect the outcome of its operations. These flags are

stored in the condition status (CS) field of the status register.

1.1.2 THREE PORT REGISTER FILE

The MAS281 architecture has been optimised for both real

time l/O and arithmetic intensive operations. Two key features

of this architecture which contribute to the overall high

performance of the MAS281 are; a barrel shifter and a parallel

multiplier/accumulator. These subsystems allow the MAS281

to perform multi-bit shifts, multiplications, divisions, and

normalisations in a fraction of the clock cycles required on

machines not having such resources. This is especially true of

floating-point operations, in which the MAS281 excels. Such

operations constitute 16% of the Digital Avionics Instruction

Set (DAIS) mix and a generally much higher percentage of

many signal processing algorithms, therefore having a

significant impact on system performance.

In accordance with MIL-STD-1750A, the MAS281 can

access a 64K-word address space. With the addition of an

external MA31751 chip configured as a Memory Management

A 24-word by 16-bit wide register file is used to store

operands, addresses, base pointers, stack pointers, indexes,

and temporary values. Registers R0 through R15 are general

purpose and user accessible in accordance with MIL-STD-

1750A; remaining registers are accessible only by microcode.

Wrap-around concatenation of R0 through R15 allows 32- and

48-bit operands to be stored. The three-port architecture

allows two 16-bit operands to be read and a third 16-bit

operand to be written simultaneously.

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