SLA7042 Ver la hoja de datos (PDF) - Allegro MicroSystems

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SLA7042

MICROSTEPPING, UNIPOLAR PWM, HIGH-CURRENT MOTOR CONTROLLER/DRIVER

Allegro MicroSystems 

SLA7042M AND SLA7044M

MICROSTEPPING,

UNIPOLAR PWM, HIGH-CURRENT

MOTOR CONTROLLER/DRIVERS

Vb

R1

V DD

TO OTHER CHANNEL

(OPTIONAL)

H = OFF

Z = REFERENCE

L = ENABLE DATA

D/A

V REF/EN

R2

......

FROM µP

111...1 = OFF

000...0 = ENABLE DATA

Dwg. EK-012

FIGURE 3. ␣COMPLETE CONTROL

SERIAL DATA INPUT

The serial DATA input port is enabled (active low) by

the REFERENCE/ENABLE input. When VREF/EN is be-

tween 0.4 V and 2.5 V, information on the DATA input is

read into the shift register on each high-to-low transition of

the CLOCK.

There are four bits: the first bit entered controls the

motor phase — a high level enables OUTA or OUTB, a low

level enables OUTA or OUTB. The next three bits set the

step reference voltage ratio and PWM OFF time as shown

in the Characteristics Tables — the least-significant bit first

and the most-significant bit last.

Data written into the serial data port is latched and

becomes active on a high-to-low transition at STROBE.

LOAD CURRENT

(NOT TO SCALE)

0

VDD

VDD - 1 V

2.5 V

REFERENCE/ENABLE

0

VDD

CLOCK

0

VDD

SERIAL DATA

0

VDD

STROBE

0

DISABLED

ENTER

DATA

3.1 µs

MIN

MOTOR PWM OPERATION

0010

= 20%

DON'T CARE

DATA LATCHED

0100

= 40%

FIGURE 4. ␣TIMING RELATIONSHIPS

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

Dwg. WK-003

™

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